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Diffstat (limited to 'dot_product/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sta.rpt')
| -rw-r--r-- | dot_product/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sta.rpt | 10440 |
1 files changed, 10440 insertions, 0 deletions
diff --git a/dot_product/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sta.rpt b/dot_product/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sta.rpt new file mode 100644 index 0000000..87ac1ea --- /dev/null +++ b/dot_product/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sta.rpt @@ -0,0 +1,10440 @@ +TimeQuest Timing Analyzer report for DE0_D5M +Mon Mar 17 11:17:31 2014 +Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. SDC File List + 5. Clocks + 6. Slow 1200mV 85C Model Fmax Summary + 7. Timing Closure Recommendations + 8. Slow 1200mV 85C Model Setup Summary + 9. Slow 1200mV 85C Model Hold Summary + 10. Slow 1200mV 85C Model Recovery Summary + 11. Slow 1200mV 85C Model Removal Summary + 12. Slow 1200mV 85C Model Minimum Pulse Width Summary + 13. Slow 1200mV 85C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' + 14. Slow 1200mV 85C Model Setup: 'CLOCK_50' + 15. Slow 1200mV 85C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' + 16. Slow 1200mV 85C Model Hold: 'CLOCK_50' + 17. Slow 1200mV 85C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' + 18. Slow 1200mV 85C Model Recovery: 'CLOCK_50' + 19. Slow 1200mV 85C Model Removal: 'CLOCK_50' + 20. Slow 1200mV 85C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' + 21. Slow 1200mV 85C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' + 22. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50' + 23. Setup Times + 24. Hold Times + 25. Clock to Output Times + 26. Minimum Clock to Output Times + 27. Propagation Delay + 28. Minimum Propagation Delay + 29. Output Enable Times + 30. Minimum Output Enable Times + 31. Output Disable Times + 32. Minimum Output Disable Times + 33. MTBF Summary + 34. Synchronizer Summary + 35. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years + 36. Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years + 37. Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years + 38. Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years + 39. Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years + 40. Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years + 41. Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years + 42. Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years + 43. Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years + 44. Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years + 45. Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years + 46. Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years + 47. Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years + 48. Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years + 49. Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years + 50. Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years + 51. Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years + 52. Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years + 53. Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years + 54. Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years + 55. Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years + 56. Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years + 57. Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years + 58. Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years + 59. Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years + 60. Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years + 61. Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years + 62. Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years + 63. Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years + 64. Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years + 65. Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years + 66. Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years + 67. Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years + 68. Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years + 69. Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years + 70. Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years + 71. Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years + 72. Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years + 73. Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years + 74. Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years + 75. Slow 1200mV 0C Model Fmax Summary + 76. Slow 1200mV 0C Model Setup Summary + 77. Slow 1200mV 0C Model Hold Summary + 78. Slow 1200mV 0C Model Recovery Summary + 79. Slow 1200mV 0C Model Removal Summary + 80. Slow 1200mV 0C Model Minimum Pulse Width Summary + 81. Slow 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' + 82. Slow 1200mV 0C Model Setup: 'CLOCK_50' + 83. Slow 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' + 84. Slow 1200mV 0C Model Hold: 'CLOCK_50' + 85. Slow 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' + 86. Slow 1200mV 0C Model Recovery: 'CLOCK_50' + 87. Slow 1200mV 0C Model Removal: 'CLOCK_50' + 88. Slow 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' + 89. Slow 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' + 90. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' + 91. Setup Times + 92. Hold Times + 93. Clock to Output Times + 94. Minimum Clock to Output Times + 95. Propagation Delay + 96. Minimum Propagation Delay + 97. Output Enable Times + 98. Minimum Output Enable Times + 99. Output Disable Times +100. Minimum Output Disable Times +101. MTBF Summary +102. Synchronizer Summary +103. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years +104. Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years +105. Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years +106. Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years +107. Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years +108. Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years +109. Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years +110. Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years +111. Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years +112. Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years +113. Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years +114. Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years +115. Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years +116. Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years +117. Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years +118. Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years +119. Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years +120. Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years +121. Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years +122. Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years +123. Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years +124. Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years +125. Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years +126. Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years +127. Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years +128. Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years +129. Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years +130. Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years +131. Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years +132. Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years +133. Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years +134. Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years +135. Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years +136. Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years +137. Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years +138. Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years +139. Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years +140. Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years +141. Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years +142. Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years +143. Fast 1200mV 0C Model Setup Summary +144. Fast 1200mV 0C Model Hold Summary +145. Fast 1200mV 0C Model Recovery Summary +146. Fast 1200mV 0C Model Removal Summary +147. Fast 1200mV 0C Model Minimum Pulse Width Summary +148. Fast 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' +149. Fast 1200mV 0C Model Setup: 'CLOCK_50' +150. Fast 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' +151. Fast 1200mV 0C Model Hold: 'CLOCK_50' +152. Fast 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' +153. Fast 1200mV 0C Model Recovery: 'CLOCK_50' +154. Fast 1200mV 0C Model Removal: 'CLOCK_50' +155. Fast 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' +156. Fast 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' +157. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' +158. Setup Times +159. Hold Times +160. Clock to Output Times +161. Minimum Clock to Output Times +162. Propagation Delay +163. Minimum Propagation Delay +164. Output Enable Times +165. Minimum Output Enable Times +166. Output Disable Times +167. Minimum Output Disable Times +168. MTBF Summary +169. Synchronizer Summary +170. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years +171. Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years +172. Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years +173. Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years +174. Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years +175. Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years +176. Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years +177. Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years +178. Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years +179. Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years +180. Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years +181. Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years +182. Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years +183. Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years +184. Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years +185. Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years +186. Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years +187. Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years +188. Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years +189. Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years +190. Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years +191. Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years +192. Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years +193. Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years +194. Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years +195. Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years +196. Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years +197. Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years +198. Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years +199. Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years +200. Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years +201. Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years +202. Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years +203. Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years +204. Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years +205. Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years +206. Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years +207. Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years +208. Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years +209. Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years +210. Multicorner Timing Analysis Summary +211. Setup Times +212. Hold Times +213. Clock to Output Times +214. Minimum Clock to Output Times +215. Propagation Delay +216. Minimum Propagation Delay +217. Board Trace Model Assignments +218. Input Transition Times +219. Slow Corner Signal Integrity Metrics +220. Fast Corner Signal Integrity Metrics +221. Setup Transfers +222. Hold Transfers +223. Recovery Transfers +224. Removal Transfers +225. Report TCCS +226. Report RSKM +227. Unconstrained Paths +228. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++--------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++--------------------+-----------------------------------------------------+ +; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Full Version ; +; Revision Name ; DE0_D5M ; +; Device Family ; Cyclone III ; +; Device Name ; EP3C16F484C6 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++--------------------+-----------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; < 0.1% ; +; Processors 5-8 ; 0.0% ; ++----------------------------+-------------+ + + ++---------------------------------------------------+ +; SDC File List ; ++---------------+--------+--------------------------+ +; SDC File Path ; Status ; Read at ; ++---------------+--------+--------------------------+ +; DE0_D5M.sdc ; OK ; Mon Mar 17 11:17:29 2014 ; ++---------------+--------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++-----------------------------------------------------+-----------+--------+-----------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------+-------------------------------------------------------+---------------------------------------------------------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++-----------------------------------------------------+-----------+--------+-----------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------+-------------------------------------------------------+---------------------------------------------------------+ +; CLOCK_50 ; Base ; 20.000 ; 50.0 MHz ; 0.000 ; 10.000 ; ; ; ; ; ; ; ; ; ; ; { CLOCK_50 } ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 8.000 ; 125.0 MHz ; 0.000 ; 4.000 ; 50.00 ; 2 ; 5 ; ; ; ; ; false ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|inclk[0] ; { inst|u6|altpll_component|auto_generated|pll1|clk[0] } ; +; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 8.000 ; 125.0 MHz ; -2.600 ; 1.400 ; 50.00 ; 2 ; 5 ; -117.0 ; ; ; ; false ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|inclk[0] ; { inst|u6|altpll_component|auto_generated|pll1|clk[1] } ; ++-----------------------------------------------------+-----------+--------+-----------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------+-------------------------------------------------------+---------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++------------+-----------------+-----------------------------------------------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+-----------------------------------------------------+------+ +; 174.31 MHz ; 174.31 MHz ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; +; 192.01 MHz ; 192.01 MHz ; CLOCK_50 ; ; ++------------+-----------------+-----------------------------------------------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + +---------------------------------- +; Timing Closure Recommendations ; +---------------------------------- +HTML report is unavailable in plain text report export. + + ++------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Setup Summary ; ++-----------------------------------------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+--------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -0.490 ; -24.984 ; +; CLOCK_50 ; 14.792 ; 0.000 ; ++-----------------------------------------------------+--------+---------------+ + + ++-----------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold Summary ; ++-----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+-------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.332 ; 0.000 ; +; CLOCK_50 ; 0.358 ; 0.000 ; ++-----------------------------------------------------+-------+---------------+ + + ++------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Recovery Summary ; ++-----------------------------------------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+--------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -1.484 ; -348.952 ; +; CLOCK_50 ; 14.000 ; 0.000 ; ++-----------------------------------------------------+--------+---------------+ + + ++-----------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Removal Summary ; ++-----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+-------+---------------+ +; CLOCK_50 ; 1.548 ; 0.000 ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.100 ; 0.000 ; ++-----------------------------------------------------+-------+---------------+ + + ++-----------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; ++-----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+-------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.733 ; 0.000 ; +; CLOCK_50 ; 9.580 ; 0.000 ; ++-----------------------------------------------------+-------+---------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; -0.490 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 2.298 ; +; -0.490 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 2.298 ; +; -0.452 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.545 ; 1.922 ; +; -0.452 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.545 ; 1.922 ; +; -0.452 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.545 ; 1.922 ; +; -0.452 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.545 ; 1.922 ; +; -0.452 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.545 ; 1.922 ; +; -0.452 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.545 ; 1.922 ; +; -0.452 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.545 ; 1.922 ; +; -0.452 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.545 ; 1.922 ; +; -0.452 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.545 ; 1.922 ; +; -0.452 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.545 ; 1.922 ; +; -0.452 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.545 ; 1.922 ; +; -0.452 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.545 ; 1.922 ; +; -0.452 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.545 ; 1.922 ; +; -0.452 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.545 ; 1.922 ; +; -0.452 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.545 ; 1.922 ; +; -0.427 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 2.235 ; +; -0.427 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.207 ; 2.235 ; +; -0.384 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.217 ; 2.182 ; +; -0.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.209 ; +; -0.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.209 ; +; -0.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.209 ; +; -0.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.209 ; +; -0.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.209 ; +; -0.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.209 ; +; -0.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.209 ; +; -0.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.209 ; +; -0.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.209 ; +; -0.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.209 ; +; -0.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.209 ; +; -0.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.209 ; +; -0.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.209 ; +; -0.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.209 ; +; -0.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.209 ; +; -0.344 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.172 ; +; -0.344 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.172 ; +; -0.344 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.172 ; +; -0.344 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.172 ; +; -0.344 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.172 ; +; -0.344 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.172 ; +; -0.344 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.172 ; +; -0.344 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.172 ; +; -0.344 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.172 ; +; -0.344 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.172 ; +; -0.344 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.172 ; +; -0.344 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.172 ; +; -0.344 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.172 ; +; -0.344 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.172 ; +; -0.344 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.187 ; 2.172 ; +; -0.215 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.211 ; 2.019 ; +; -0.215 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.211 ; 2.019 ; +; -0.215 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.211 ; 2.019 ; +; -0.215 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.211 ; 2.019 ; +; -0.215 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.211 ; 2.019 ; +; -0.215 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.211 ; 2.019 ; +; -0.215 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.211 ; 2.019 ; +; -0.215 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.211 ; 2.019 ; +; -0.215 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.211 ; 2.019 ; +; -0.215 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.211 ; 2.019 ; +; -0.215 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.211 ; 2.019 ; +; -0.215 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.211 ; 2.019 ; +; -0.215 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.211 ; 2.019 ; +; -0.215 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.211 ; 2.019 ; +; -0.215 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.211 ; 2.019 ; +; -0.151 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.203 ; 1.963 ; +; -0.151 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.203 ; 1.963 ; +; -0.151 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.203 ; 1.963 ; +; -0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.186 ; 1.972 ; +; -0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.186 ; 1.972 ; +; -0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.186 ; 1.972 ; +; -0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.186 ; 1.972 ; +; -0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.186 ; 1.972 ; +; -0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.186 ; 1.972 ; +; -0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.186 ; 1.972 ; +; -0.085 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.176 ; 1.924 ; +; -0.085 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.176 ; 1.924 ; +; -0.085 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.176 ; 1.924 ; +; -0.059 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.216 ; 1.858 ; +; -0.059 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.216 ; 1.858 ; +; -0.059 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.216 ; 1.858 ; +; 2.263 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.100 ; 5.652 ; +; 2.263 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.100 ; 5.652 ; +; 2.263 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.291 ; 6.043 ; +; 2.269 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.260 ; 6.006 ; +; 2.269 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.260 ; 6.006 ; +; 2.276 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.290 ; 6.029 ; +; 2.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.100 ; 5.589 ; +; 2.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.100 ; 5.589 ; +; 2.332 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.260 ; 5.943 ; +; 2.332 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.260 ; 5.943 ; +; 2.334 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.100 ; 5.581 ; +; 2.334 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.100 ; 5.581 ; +; 2.357 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.099 ; 5.559 ; +; 2.357 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.099 ; 5.559 ; +; 2.369 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.110 ; 5.536 ; +; 2.372 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.291 ; 5.934 ; +; 2.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.250 ; 5.890 ; +; 2.382 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.100 ; 5.533 ; +; 2.382 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.100 ; 5.533 ; ++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Setup: 'CLOCK_50' ; ++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 14.792 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.149 ; +; 14.792 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.149 ; +; 14.792 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.149 ; +; 14.792 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.149 ; +; 14.792 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.149 ; +; 14.792 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.149 ; +; 14.792 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.149 ; +; 14.792 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.149 ; +; 14.792 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.149 ; +; 14.792 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.149 ; +; 14.792 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.149 ; +; 14.792 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.149 ; +; 14.792 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.149 ; +; 14.801 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.140 ; +; 14.801 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.140 ; +; 14.801 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.140 ; +; 14.801 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.140 ; +; 14.801 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.140 ; +; 14.801 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.140 ; +; 14.801 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.140 ; +; 14.801 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.140 ; +; 14.801 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.140 ; +; 14.801 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.140 ; +; 14.801 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.140 ; +; 14.801 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.140 ; +; 14.801 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.140 ; +; 14.897 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.044 ; +; 14.897 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.044 ; +; 14.897 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.044 ; +; 14.897 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.044 ; +; 14.897 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.044 ; +; 14.897 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.044 ; +; 14.897 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.044 ; +; 14.897 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.044 ; +; 14.897 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.044 ; +; 14.897 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.044 ; +; 14.897 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.044 ; +; 14.897 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.044 ; +; 14.897 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.044 ; +; 14.936 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.073 ; 5.006 ; +; 14.936 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.073 ; 5.006 ; +; 14.936 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.073 ; 5.006 ; +; 14.936 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.073 ; 5.006 ; +; 14.936 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.073 ; 5.006 ; +; 14.936 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.073 ; 5.006 ; +; 14.936 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.073 ; 5.006 ; +; 14.936 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.073 ; 5.006 ; +; 14.936 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.073 ; 5.006 ; +; 14.936 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.073 ; 5.006 ; +; 14.936 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.073 ; 5.006 ; +; 14.936 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.073 ; 5.006 ; +; 14.936 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.073 ; 5.006 ; +; 14.941 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.000 ; +; 14.950 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 4.991 ; +; 14.977 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.976 ; +; 14.977 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.976 ; +; 14.977 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.976 ; +; 14.977 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.976 ; +; 14.977 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.976 ; +; 14.977 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.976 ; +; 14.977 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.976 ; +; 14.977 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.976 ; +; 14.977 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.976 ; +; 14.977 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.976 ; +; 14.977 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.976 ; +; 14.977 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.976 ; +; 14.977 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.976 ; +; 14.977 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.976 ; +; 14.977 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.976 ; +; 14.977 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.976 ; +; 14.980 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.973 ; +; 14.980 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.973 ; +; 14.980 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.973 ; +; 14.980 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.973 ; +; 14.980 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.973 ; +; 14.980 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.973 ; +; 14.980 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.973 ; +; 14.980 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.973 ; +; 14.980 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.973 ; +; 14.980 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.973 ; +; 14.980 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.973 ; +; 14.980 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.973 ; +; 14.980 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.973 ; +; 14.980 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.973 ; +; 14.980 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.973 ; +; 14.980 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.062 ; 4.973 ; +; 15.017 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.939 ; +; 15.017 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.939 ; +; 15.017 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.939 ; +; 15.017 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.939 ; +; 15.017 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.939 ; +; 15.017 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.939 ; +; 15.017 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.939 ; +; 15.017 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.939 ; +; 15.017 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.939 ; +; 15.017 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.939 ; +; 15.017 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.939 ; +; 15.017 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.939 ; +; 15.017 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.939 ; +; 15.017 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.059 ; 4.939 ; ++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; 0.332 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.425 ; 0.914 ; +; 0.341 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.378 ; 0.906 ; +; 0.343 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.577 ; +; 0.343 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.577 ; +; 0.344 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.378 ; 0.910 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.577 ; +; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 0.577 ; +; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 0.577 ; +; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 0.577 ; +; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 0.577 ; +; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 0.577 ; +; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 0.577 ; +; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 0.577 ; +; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 0.577 ; +; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 0.577 ; +; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 0.577 ; +; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 0.577 ; +; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 0.577 ; +; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 0.577 ; +; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 0.577 ; +; 0.348 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.374 ; 0.909 ; +; 0.357 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 0.590 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.592 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.577 ; +; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.577 ; +; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.577 ; +; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.577 ; +; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.577 ; +; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.577 ; +; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.577 ; +; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.594 ; +; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 0.593 ; +; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 0.593 ; +; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 0.593 ; +; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.593 ; +; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.580 ; +; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.580 ; +; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.580 ; +; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.593 ; +; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 0.594 ; +; 0.362 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 0.595 ; +; 0.362 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 0.594 ; +; 0.371 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.425 ; 0.953 ; +; 0.372 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.590 ; +; 0.372 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.590 ; +; 0.373 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.592 ; +; 0.373 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.592 ; +; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.592 ; +; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[15] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.593 ; +; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[17] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.593 ; +; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|BA[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.593 ; +; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.608 ; +; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REFRESH ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_refresh ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.593 ; +; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_done ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.593 ; +; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.593 ; +; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.592 ; +; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.593 ; +; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[6] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.593 ; +; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.594 ; +; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[16] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[8] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.593 ; +; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.594 ; +; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|RAS_N ; DE0_D5M:inst|Sdram_Control_4Port:u7|RAS_N ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.594 ; +; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 0.608 ; +; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_shift[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.594 ; +; 0.376 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 0.609 ; +; 0.376 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 0.594 ; +; 0.376 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.595 ; +; 0.377 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 0.610 ; +; 0.378 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.597 ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold: 'CLOCK_50' ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.577 ; +; 0.361 ; DE0_D5M:inst|Reset_Delay:u2|Cont[0] ; DE0_D5M:inst|Reset_Delay:u2|Cont[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.580 ; +; 0.361 ; ps2:inst6|clk_div[0] ; ps2:inst6|clk_div[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.580 ; +; 0.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.593 ; +; 0.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.593 ; +; 0.382 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.038 ; 0.577 ; +; 0.385 ; DE0_D5M:inst|rClk[0] ; DE0_D5M:inst|rClk[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.038 ; 0.580 ; +; 0.389 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.608 ; +; 0.390 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.609 ; +; 0.434 ; ps2:inst6|clk_div[8] ; ps2:inst6|clk_div[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.038 ; 0.629 ; +; 0.523 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.742 ; +; 0.550 ; ps2:inst6|clk_div[4] ; ps2:inst6|clk_div[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.769 ; +; 0.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.769 ; +; 0.551 ; ps2:inst6|clk_div[3] ; ps2:inst6|clk_div[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.770 ; +; 0.552 ; ps2:inst6|clk_div[2] ; ps2:inst6|clk_div[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.771 ; +; 0.553 ; ps2:inst6|clk_div[6] ; ps2:inst6|clk_div[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.772 ; +; 0.555 ; ps2:inst6|clk_div[7] ; ps2:inst6|clk_div[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.774 ; +; 0.555 ; ps2:inst6|clk_div[5] ; ps2:inst6|clk_div[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.774 ; +; 0.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.775 ; +; 0.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.775 ; +; 0.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.775 ; +; 0.557 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.776 ; +; 0.557 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.776 ; +; 0.557 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.776 ; +; 0.557 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.776 ; +; 0.557 ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.776 ; +; 0.558 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.777 ; +; 0.558 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.777 ; +; 0.558 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.777 ; +; 0.558 ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.777 ; +; 0.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.778 ; +; 0.559 ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.778 ; +; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.779 ; +; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.779 ; +; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.779 ; +; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.779 ; +; 0.561 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.780 ; +; 0.561 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.780 ; +; 0.561 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.780 ; +; 0.562 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.781 ; +; 0.562 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.781 ; +; 0.562 ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.781 ; +; 0.562 ; ps2:inst6|clk_div[0] ; ps2:inst6|clk_div[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.781 ; +; 0.563 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.782 ; +; 0.564 ; ps2:inst6|clk_div[1] ; ps2:inst6|clk_div[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.783 ; +; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.788 ; +; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.788 ; +; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.788 ; +; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.788 ; +; 0.570 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.789 ; +; 0.570 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.789 ; +; 0.570 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.788 ; +; 0.570 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.788 ; +; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.789 ; +; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.789 ; +; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[14] ; DE0_D5M:inst|Reset_Delay:u2|Cont[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.789 ; +; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.789 ; +; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.789 ; +; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.789 ; +; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.789 ; +; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.789 ; +; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.789 ; +; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.789 ; +; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.790 ; +; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.790 ; +; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.790 ; +; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.790 ; +; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.790 ; +; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.790 ; +; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.790 ; +; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.790 ; +; 0.572 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.790 ; +; 0.572 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.790 ; +; 0.572 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.791 ; +; 0.572 ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.791 ; +; 0.572 ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.791 ; +; 0.572 ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.791 ; +; 0.572 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.791 ; +; 0.572 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.791 ; +; 0.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.791 ; +; 0.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.791 ; +; 0.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.791 ; +; 0.573 ; DE0_D5M:inst|Reset_Delay:u2|Cont[9] ; DE0_D5M:inst|Reset_Delay:u2|Cont[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.792 ; +; 0.574 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.792 ; +; 0.574 ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.793 ; +; 0.574 ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.793 ; +; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.793 ; +; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.793 ; +; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.793 ; +; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.061 ; 0.793 ; +; 0.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.800 ; +; 0.586 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.805 ; +; 0.587 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.806 ; +; 0.587 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.806 ; +; 0.589 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.808 ; +; 0.590 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.809 ; +; 0.592 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.811 ; +; 0.697 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.062 ; 0.916 ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; -1.484 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.296 ; 3.137 ; +; -1.484 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.296 ; 3.137 ; +; -1.484 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.296 ; 3.137 ; +; -1.484 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.296 ; 3.137 ; +; -1.484 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.296 ; 3.137 ; +; -1.484 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.296 ; 3.137 ; +; -1.484 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.296 ; 3.137 ; +; -1.484 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.296 ; 3.137 ; +; -1.484 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.296 ; 3.137 ; +; -1.484 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.296 ; 3.137 ; +; -1.484 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.296 ; 3.137 ; +; -1.484 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.296 ; 3.137 ; +; -1.484 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.296 ; 3.137 ; +; -1.484 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.296 ; 3.137 ; +; -1.484 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.296 ; 3.137 ; +; -1.484 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.296 ; 3.137 ; +; -1.474 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.288 ; 3.135 ; +; -1.474 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.288 ; 3.135 ; +; -1.474 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.288 ; 3.135 ; +; -1.474 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.288 ; 3.135 ; +; -1.474 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.288 ; 3.135 ; +; -1.474 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.288 ; 3.135 ; +; -1.474 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.288 ; 3.135 ; +; -1.474 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.288 ; 3.135 ; +; -1.474 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.288 ; 3.135 ; +; -1.474 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.288 ; 3.135 ; +; -1.474 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.288 ; 3.135 ; +; -1.474 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.288 ; 3.135 ; +; -1.474 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.288 ; 3.135 ; +; -1.474 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.288 ; 3.135 ; +; -1.474 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.288 ; 3.135 ; +; -1.474 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.288 ; 3.135 ; +; -1.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.293 ; 3.179 ; +; -1.414 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.285 ; 3.177 ; +; -1.333 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.544 ; 2.804 ; +; -1.333 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.544 ; 2.804 ; +; -1.333 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.544 ; 2.804 ; +; -1.333 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.544 ; 2.804 ; +; -1.333 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.544 ; 2.804 ; +; -1.333 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.544 ; 2.804 ; +; -1.332 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.543 ; 2.804 ; +; -1.332 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.543 ; 2.804 ; +; -1.332 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.543 ; 2.804 ; +; -1.332 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.543 ; 2.804 ; +; -1.332 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.543 ; 2.804 ; +; -1.332 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.543 ; 2.804 ; +; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.549 ; 2.783 ; +; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.549 ; 2.783 ; +; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.551 ; 2.781 ; +; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.551 ; 2.781 ; +; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.551 ; 2.781 ; +; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.551 ; 2.781 ; +; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.551 ; 2.781 ; +; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.549 ; 2.783 ; +; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.549 ; 2.783 ; +; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.549 ; 2.783 ; +; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.549 ; 2.783 ; +; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.549 ; 2.783 ; +; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.549 ; 2.783 ; +; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.549 ; 2.783 ; +; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.549 ; 2.783 ; +; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.549 ; 2.783 ; +; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.549 ; 2.783 ; +; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.550 ; 2.781 ; +; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.550 ; 2.781 ; +; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.550 ; 2.781 ; +; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.550 ; 2.781 ; +; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.550 ; 2.781 ; +; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.550 ; 2.781 ; +; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.550 ; 2.781 ; +; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.550 ; 2.781 ; +; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.550 ; 2.781 ; +; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.550 ; 2.781 ; +; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.550 ; 2.781 ; +; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.548 ; 2.783 ; +; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.548 ; 2.783 ; +; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.548 ; 2.783 ; +; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.548 ; 2.783 ; +; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.548 ; 2.783 ; +; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.548 ; 2.783 ; +; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.548 ; 2.783 ; +; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.550 ; 2.781 ; +; -1.310 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.538 ; 2.787 ; +; -1.310 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.538 ; 2.787 ; +; -1.310 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.538 ; 2.787 ; +; -1.310 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.539 ; 2.786 ; +; -1.310 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.539 ; 2.786 ; +; -1.310 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.538 ; 2.787 ; +; -1.310 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.539 ; 2.786 ; +; -1.310 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.539 ; 2.786 ; +; -1.310 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.539 ; 2.786 ; +; -1.310 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.539 ; 2.786 ; +; -1.310 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.539 ; 2.786 ; +; -1.310 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.539 ; 2.786 ; +; -1.310 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.537 ; 2.788 ; +; -1.309 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.538 ; 2.786 ; +; -1.309 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.538 ; 2.786 ; +; -1.309 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.538 ; 2.786 ; +; -1.309 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.538 ; 2.786 ; +; -1.309 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.538 ; 2.786 ; ++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Recovery: 'CLOCK_50' ; ++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 14.000 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.802 ; 5.213 ; +; 14.009 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.802 ; 5.204 ; +; 14.105 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.802 ; 5.108 ; +; 14.144 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.801 ; 5.070 ; +; 14.243 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.802 ; 4.970 ; +; 14.287 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.801 ; 4.927 ; +; 14.289 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.801 ; 4.925 ; +; 14.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.801 ; 4.917 ; +; 14.384 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.801 ; 4.830 ; +; 14.392 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.801 ; 4.822 ; +; 14.523 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.801 ; 4.691 ; +; 14.524 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.801 ; 4.690 ; +; 14.531 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.801 ; 4.683 ; +; 14.532 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.801 ; 4.682 ; +; 14.629 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.801 ; 4.585 ; +; 14.766 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.801 ; 4.448 ; +; 14.836 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.802 ; 4.377 ; +; 14.979 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.802 ; 4.234 ; +; 15.020 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.931 ; +; 15.020 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.931 ; +; 15.020 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.931 ; +; 15.020 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.931 ; +; 15.020 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.931 ; +; 15.020 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.931 ; +; 15.020 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.931 ; +; 15.020 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.931 ; +; 15.020 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.931 ; +; 15.020 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.931 ; +; 15.020 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.931 ; +; 15.020 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.931 ; +; 15.020 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.931 ; +; 15.020 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.931 ; +; 15.020 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.931 ; +; 15.020 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.931 ; +; 15.029 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.922 ; +; 15.029 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.922 ; +; 15.029 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.922 ; +; 15.029 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.922 ; +; 15.029 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.922 ; +; 15.029 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.922 ; +; 15.029 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.922 ; +; 15.029 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.922 ; +; 15.029 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.922 ; +; 15.029 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.922 ; +; 15.029 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.922 ; +; 15.029 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.922 ; +; 15.029 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.922 ; +; 15.029 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.922 ; +; 15.029 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.922 ; +; 15.029 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.922 ; +; 15.041 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.802 ; 4.172 ; +; 15.050 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.802 ; 4.163 ; +; 15.090 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.802 ; 4.123 ; +; 15.125 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.826 ; +; 15.125 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.826 ; +; 15.125 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.826 ; +; 15.125 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.826 ; +; 15.125 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.826 ; +; 15.125 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.826 ; +; 15.125 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.826 ; +; 15.125 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.826 ; +; 15.125 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.826 ; +; 15.125 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.826 ; +; 15.125 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.826 ; +; 15.125 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.826 ; +; 15.125 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.826 ; +; 15.125 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.826 ; +; 15.125 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.826 ; +; 15.125 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.826 ; +; 15.142 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.802 ; 4.071 ; +; 15.146 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.802 ; 4.067 ; +; 15.164 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.788 ; +; 15.164 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.788 ; +; 15.164 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.788 ; +; 15.164 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.788 ; +; 15.164 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.788 ; +; 15.164 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.788 ; +; 15.164 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.788 ; +; 15.164 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.788 ; +; 15.164 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.788 ; +; 15.164 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.788 ; +; 15.164 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.788 ; +; 15.164 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.788 ; +; 15.164 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.788 ; +; 15.164 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.788 ; +; 15.164 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.788 ; +; 15.164 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.063 ; 4.788 ; +; 15.263 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.688 ; +; 15.263 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.688 ; +; 15.263 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.688 ; +; 15.263 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.688 ; +; 15.263 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.688 ; +; 15.263 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.688 ; +; 15.263 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.688 ; +; 15.263 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.688 ; +; 15.263 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.688 ; +; 15.263 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.688 ; +; 15.263 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.688 ; +; 15.263 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.688 ; +; 15.263 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.064 ; 4.688 ; ++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Removal: 'CLOCK_50' ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 1.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.060 ; 1.765 ; +; 1.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.060 ; 1.765 ; +; 1.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.060 ; 1.765 ; +; 1.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.060 ; 1.765 ; +; 1.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.060 ; 1.765 ; +; 1.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.060 ; 1.765 ; +; 1.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.060 ; 1.765 ; +; 1.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.060 ; 1.765 ; +; 1.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.060 ; 1.765 ; +; 1.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.060 ; 1.765 ; +; 1.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.060 ; 1.765 ; +; 1.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.060 ; 1.765 ; +; 1.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.060 ; 1.765 ; +; 1.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.060 ; 1.765 ; +; 1.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.060 ; 1.765 ; +; 1.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.060 ; 1.765 ; +; 1.764 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.060 ; 1.981 ; +; 1.764 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.060 ; 1.981 ; +; 1.764 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.060 ; 1.981 ; +; 1.764 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.060 ; 1.981 ; +; 1.764 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.060 ; 1.981 ; +; 1.764 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.060 ; 1.981 ; +; 1.764 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.060 ; 1.981 ; +; 1.764 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.060 ; 1.981 ; +; 1.764 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.060 ; 1.981 ; +; 1.764 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.060 ; 1.981 ; +; 1.764 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.060 ; 1.981 ; +; 1.764 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.060 ; 1.981 ; +; 1.764 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.060 ; 1.981 ; +; 1.764 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.060 ; 1.981 ; +; 1.764 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.060 ; 1.981 ; +; 1.764 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.060 ; 1.981 ; +; 2.181 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.074 ; 2.412 ; +; 2.181 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.074 ; 2.412 ; +; 2.181 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.074 ; 2.412 ; +; 2.181 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.074 ; 2.412 ; +; 2.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.074 ; 2.432 ; +; 2.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.074 ; 2.432 ; +; 2.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.074 ; 2.432 ; +; 2.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.074 ; 2.432 ; +; 2.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.074 ; 2.432 ; +; 2.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.074 ; 2.432 ; +; 2.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.074 ; 2.432 ; +; 2.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.074 ; 2.432 ; +; 2.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.074 ; 2.432 ; +; 2.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.074 ; 2.432 ; +; 2.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.074 ; 2.432 ; +; 2.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.074 ; 2.432 ; +; 2.263 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.075 ; 2.495 ; +; 2.263 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.075 ; 2.495 ; +; 2.263 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.075 ; 2.495 ; +; 2.263 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.075 ; 2.495 ; +; 2.263 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.075 ; 2.495 ; +; 2.263 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.075 ; 2.495 ; +; 2.263 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.075 ; 2.495 ; +; 2.263 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.075 ; 2.495 ; +; 2.263 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.075 ; 2.495 ; +; 2.263 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.075 ; 2.495 ; +; 2.263 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.075 ; 2.495 ; +; 2.263 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.075 ; 2.495 ; +; 2.263 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.075 ; 2.495 ; +; 2.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 2.706 ; +; 2.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 2.706 ; +; 2.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 2.706 ; +; 2.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 2.706 ; +; 2.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 2.706 ; +; 2.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 2.706 ; +; 2.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 2.706 ; +; 2.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 2.706 ; +; 2.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 2.706 ; +; 2.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 2.706 ; +; 2.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 2.706 ; +; 2.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 2.706 ; +; 2.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 2.706 ; +; 2.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.063 ; 2.706 ; +; 2.550 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 0.000 ; -0.664 ; 2.043 ; +; 2.758 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 0.000 ; -0.664 ; 2.251 ; +; 2.969 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 3.198 ; +; 2.969 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 3.198 ; +; 2.969 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 3.198 ; +; 2.969 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 3.198 ; +; 2.969 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 3.198 ; +; 2.969 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 3.198 ; +; 2.969 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 3.198 ; +; 2.969 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 3.198 ; +; 2.969 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 3.198 ; +; 2.969 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 3.198 ; +; 2.969 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 3.198 ; +; 2.969 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 3.198 ; +; 2.969 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 3.198 ; +; 2.969 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 3.198 ; +; 2.969 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 3.198 ; +; 2.969 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 3.198 ; +; 3.123 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.059 ; 3.339 ; +; 3.123 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.059 ; 3.339 ; +; 3.123 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.059 ; 3.339 ; +; 3.123 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.059 ; 3.339 ; +; 3.123 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.059 ; 3.339 ; +; 3.123 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.059 ; 3.339 ; +; 3.123 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.059 ; 3.339 ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; 4.100 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.671 ; 2.586 ; +; 4.100 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.671 ; 2.586 ; +; 4.118 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.680 ; 2.595 ; +; 4.118 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.680 ; 2.595 ; +; 4.118 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.680 ; 2.595 ; +; 4.118 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.680 ; 2.595 ; +; 4.118 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.680 ; 2.595 ; +; 4.118 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.680 ; 2.595 ; +; 4.118 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.680 ; 2.595 ; +; 4.118 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.680 ; 2.595 ; +; 4.118 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.680 ; 2.595 ; +; 4.118 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.680 ; 2.595 ; +; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.591 ; +; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.591 ; +; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.591 ; +; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.591 ; +; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.591 ; +; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.591 ; +; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.692 ; 2.589 ; +; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.692 ; 2.589 ; +; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.692 ; 2.589 ; +; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.692 ; 2.589 ; +; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.692 ; 2.589 ; +; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.591 ; +; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.591 ; +; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.692 ; 2.589 ; +; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.692 ; 2.589 ; +; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.591 ; +; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.690 ; 2.591 ; +; 4.127 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.691 ; 2.593 ; +; 4.127 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.691 ; 2.593 ; +; 4.127 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.691 ; 2.593 ; +; 4.127 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.691 ; 2.593 ; +; 4.127 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.691 ; 2.593 ; +; 4.127 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.691 ; 2.593 ; +; 4.128 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.596 ; +; 4.128 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.596 ; +; 4.128 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.596 ; +; 4.128 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.596 ; +; 4.128 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.596 ; +; 4.128 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.596 ; +; 4.128 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.596 ; +; 4.128 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.689 ; 2.596 ; +; 4.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.696 ; 2.590 ; +; 4.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.696 ; 2.590 ; +; 4.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.696 ; 2.590 ; +; 4.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.696 ; 2.590 ; +; 4.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.696 ; 2.590 ; +; 4.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.696 ; 2.590 ; +; 4.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.696 ; 2.590 ; +; 4.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.696 ; 2.590 ; +; 4.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.696 ; 2.590 ; +; 4.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.696 ; 2.590 ; +; 4.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.696 ; 2.590 ; +; 4.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.696 ; 2.590 ; +; 4.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.696 ; 2.590 ; +; 4.137 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.686 ; 2.608 ; +; 4.137 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.686 ; 2.608 ; +; 4.137 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.686 ; 2.608 ; +; 4.137 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.686 ; 2.608 ; +; 4.137 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.686 ; 2.608 ; +; 4.137 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.686 ; 2.608 ; +; 4.137 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.686 ; 2.608 ; +; 4.137 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.686 ; 2.608 ; +; 4.137 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.686 ; 2.608 ; +; 4.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.703 ; 2.592 ; +; 4.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.703 ; 2.592 ; +; 4.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.703 ; 2.592 ; +; 4.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.703 ; 2.592 ; +; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.707 ; 2.595 ; +; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.707 ; 2.595 ; +; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.707 ; 2.595 ; +; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.707 ; 2.595 ; +; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.707 ; 2.595 ; +; 4.147 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.694 ; 2.610 ; +; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.606 ; +; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.606 ; +; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.606 ; +; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.606 ; +; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.606 ; +; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.606 ; +; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.606 ; +; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.606 ; +; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.606 ; +; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.606 ; +; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.606 ; +; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.606 ; +; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.606 ; +; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.606 ; +; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.606 ; +; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.606 ; +; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.606 ; +; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.606 ; +; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.606 ; +; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.606 ; +; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.700 ; 2.606 ; +; 4.150 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.701 ; 2.606 ; +; 4.150 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.701 ; 2.606 ; +; 4.150 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.701 ; 2.606 ; +; 4.150 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.701 ; 2.606 ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; 3.733 ; 3.963 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; +; 3.733 ; 3.963 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0 ; +; 3.733 ; 3.963 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_we_reg ; +; 3.734 ; 3.964 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; +; 3.734 ; 3.964 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0 ; +; 3.734 ; 3.964 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_we_reg ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8] ; +; 3.745 ; 3.975 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9] ; +; 3.746 ; 3.976 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; +; 3.746 ; 3.976 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; +; 3.746 ; 3.976 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; +; 3.746 ; 3.976 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; +; 3.746 ; 3.976 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13] ; +; 3.746 ; 3.976 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14] ; +; 3.746 ; 3.976 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15] ; +; 3.746 ; 3.976 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1] ; +; 3.746 ; 3.976 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2] ; +; 3.746 ; 3.976 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3] ; +; 3.746 ; 3.976 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4] ; +; 3.746 ; 3.976 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5] ; +; 3.746 ; 3.976 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6] ; +; 3.746 ; 3.976 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7] ; +; 3.746 ; 3.976 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8] ; +; 3.746 ; 3.976 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9] ; +; 3.747 ; 3.977 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[12] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8] ; +; 3.755 ; 3.971 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9] ; +; 3.756 ; 3.972 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; +; 3.756 ; 3.972 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; +; 3.756 ; 3.972 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; +; 3.756 ; 3.972 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; +; 3.756 ; 3.972 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; +; 3.756 ; 3.972 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; +; 3.756 ; 3.972 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; +; 3.756 ; 3.972 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1] ; +; 3.756 ; 3.972 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2] ; +; 3.756 ; 3.972 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; +; 3.756 ; 3.972 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; +; 3.756 ; 3.972 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; +; 3.756 ; 3.972 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; +; 3.756 ; 3.972 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; +; 3.756 ; 3.972 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; +; 3.756 ; 3.972 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1] ; ++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50' ; ++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+ +; 9.580 ; 9.764 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; +; 9.580 ; 9.764 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|rClk[0] ; +; 9.580 ; 9.764 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[8] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; +; 9.592 ; 9.776 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[0] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[14] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[1] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[9] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|oRST_1 ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[0] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[1] ; +; 9.593 ; 9.777 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[2] ; ++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Setup Times ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; SW[*] ; CLOCK_50 ; 4.162 ; 4.886 ; Rise ; CLOCK_50 ; +; SW[0] ; CLOCK_50 ; 4.162 ; 4.886 ; Rise ; CLOCK_50 ; +; SW[1] ; CLOCK_50 ; 4.039 ; 4.609 ; Rise ; CLOCK_50 ; +; DRAM_DQ[*] ; CLOCK_50 ; 4.195 ; 4.756 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 3.989 ; 4.558 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 3.703 ; 4.276 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 3.849 ; 4.364 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 3.867 ; 4.442 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 4.195 ; 4.756 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 3.689 ; 4.201 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 3.971 ; 4.530 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 3.696 ; 4.203 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 3.713 ; 4.224 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 3.663 ; 4.241 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 3.721 ; 4.230 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 3.722 ; 4.233 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 3.874 ; 4.393 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 3.710 ; 4.224 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 3.905 ; 4.446 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------+ +; Hold Times ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ +; SW[*] ; CLOCK_50 ; -2.087 ; -2.671 ; Rise ; CLOCK_50 ; +; SW[0] ; CLOCK_50 ; -2.090 ; -2.682 ; Rise ; CLOCK_50 ; +; SW[1] ; CLOCK_50 ; -2.087 ; -2.671 ; Rise ; CLOCK_50 ; +; DRAM_DQ[*] ; CLOCK_50 ; -2.958 ; -3.503 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; -3.298 ; -3.846 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; -2.998 ; -3.549 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; -3.175 ; -3.681 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; -3.167 ; -3.731 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; -3.470 ; -4.011 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; -3.010 ; -3.503 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; -3.282 ; -3.820 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; -3.017 ; -3.504 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; -3.034 ; -3.526 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; -2.958 ; -3.514 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; -3.042 ; -3.533 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; -3.042 ; -3.534 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; -3.201 ; -3.711 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; -3.031 ; -3.526 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; -3.218 ; -3.738 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------+ +; Clock to Output Times ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; GPIO_1[*] ; CLOCK_50 ; 6.431 ; 6.267 ; Rise ; CLOCK_50 ; +; GPIO_1[14] ; CLOCK_50 ; 6.284 ; 6.232 ; Rise ; CLOCK_50 ; +; GPIO_1[20] ; CLOCK_50 ; 6.431 ; 6.267 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[*] ; CLOCK_50 ; 5.650 ; 5.688 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[0] ; CLOCK_50 ; 5.650 ; 5.688 ; Rise ; CLOCK_50 ; +; VGA_CLK ; CLOCK_50 ; 5.538 ; 5.554 ; Rise ; CLOCK_50 ; +; DRAM_ADDR[*] ; CLOCK_50 ; 3.411 ; 3.299 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[0] ; CLOCK_50 ; 3.411 ; 3.281 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[1] ; CLOCK_50 ; 3.406 ; 3.299 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[2] ; CLOCK_50 ; 3.385 ; 3.272 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[3] ; CLOCK_50 ; 3.389 ; 3.280 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[4] ; CLOCK_50 ; 3.195 ; 3.089 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[5] ; CLOCK_50 ; 3.177 ; 3.073 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[6] ; CLOCK_50 ; 2.996 ; 2.898 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[7] ; CLOCK_50 ; 3.010 ; 2.913 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[8] ; CLOCK_50 ; 3.001 ; 2.902 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[9] ; CLOCK_50 ; 2.997 ; 2.903 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[10] ; CLOCK_50 ; 3.250 ; 3.155 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[11] ; CLOCK_50 ; 2.988 ; 2.896 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_0 ; CLOCK_50 ; 3.075 ; 2.992 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_1 ; CLOCK_50 ; 3.238 ; 3.151 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CAS_N ; CLOCK_50 ; 3.180 ; 3.078 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CS_N ; CLOCK_50 ; 3.582 ; 3.529 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[*] ; CLOCK_50 ; 7.477 ; 7.147 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 5.872 ; 5.694 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 5.872 ; 5.846 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 5.578 ; 5.489 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 7.477 ; 7.147 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 5.679 ; 5.582 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 5.894 ; 5.773 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 5.858 ; 5.642 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 5.792 ; 5.739 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 5.729 ; 5.636 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 5.790 ; 5.709 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 5.922 ; 5.821 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 5.990 ; 5.797 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 6.015 ; 5.897 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 5.995 ; 5.873 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 5.870 ; 5.693 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 5.824 ; 5.740 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_LDQM ; CLOCK_50 ; 3.439 ; 3.316 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_RAS_N ; CLOCK_50 ; 3.393 ; 3.282 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_UDQM ; CLOCK_50 ; 3.336 ; 3.248 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 5.226 ; 4.902 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CLK ; CLOCK_50 ; -0.575 ; ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; +; DRAM_CLK ; CLOCK_50 ; ; -0.703 ; Fall ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; GPIO_1[*] ; CLOCK_50 ; 6.133 ; 6.078 ; Rise ; CLOCK_50 ; +; GPIO_1[14] ; CLOCK_50 ; 6.133 ; 6.078 ; Rise ; CLOCK_50 ; +; GPIO_1[20] ; CLOCK_50 ; 6.275 ; 6.112 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[*] ; CLOCK_50 ; 5.525 ; 5.556 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[0] ; CLOCK_50 ; 5.525 ; 5.556 ; Rise ; CLOCK_50 ; +; VGA_CLK ; CLOCK_50 ; 5.412 ; 5.432 ; Rise ; CLOCK_50 ; +; DRAM_ADDR[*] ; CLOCK_50 ; 2.568 ; 2.474 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[0] ; CLOCK_50 ; 2.975 ; 2.845 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[1] ; CLOCK_50 ; 2.971 ; 2.863 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[2] ; CLOCK_50 ; 2.950 ; 2.837 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[3] ; CLOCK_50 ; 2.953 ; 2.844 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[4] ; CLOCK_50 ; 2.769 ; 2.661 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[5] ; CLOCK_50 ; 2.749 ; 2.645 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[6] ; CLOCK_50 ; 2.577 ; 2.478 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[7] ; CLOCK_50 ; 2.590 ; 2.492 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[8] ; CLOCK_50 ; 2.580 ; 2.481 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[9] ; CLOCK_50 ; 2.577 ; 2.481 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[10] ; CLOCK_50 ; 2.820 ; 2.723 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[11] ; CLOCK_50 ; 2.568 ; 2.474 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_0 ; CLOCK_50 ; 2.651 ; 2.567 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_1 ; CLOCK_50 ; 2.808 ; 2.720 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CAS_N ; CLOCK_50 ; 2.751 ; 2.648 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CS_N ; CLOCK_50 ; 3.137 ; 3.081 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[*] ; CLOCK_50 ; 3.606 ; 3.480 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 3.606 ; 3.480 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 4.421 ; 4.387 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 4.079 ; 4.021 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 5.955 ; 5.620 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 4.156 ; 4.053 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 4.296 ; 4.214 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 4.136 ; 4.032 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 4.323 ; 4.259 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 3.944 ; 3.844 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 3.982 ; 3.895 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 4.106 ; 3.999 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 3.999 ; 3.903 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 4.434 ; 4.307 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 4.200 ; 4.075 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 3.878 ; 3.761 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 4.004 ; 3.940 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_LDQM ; CLOCK_50 ; 3.000 ; 2.878 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_RAS_N ; CLOCK_50 ; 2.956 ; 2.844 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_UDQM ; CLOCK_50 ; 2.901 ; 2.812 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 4.796 ; 4.472 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CLK ; CLOCK_50 ; -0.948 ; ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; +; DRAM_CLK ; CLOCK_50 ; ; -1.075 ; Fall ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++------------------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+-------+-------+--------+--------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+--------+--------+ +; SW[4] ; VGA_B[0] ; 8.598 ; 8.436 ; 9.243 ; 9.072 ; +; SW[4] ; VGA_B[1] ; 8.447 ; 8.325 ; 9.042 ; 8.914 ; +; SW[4] ; VGA_B[2] ; 8.575 ; 8.414 ; 9.221 ; 9.051 ; +; SW[4] ; VGA_B[3] ; 8.667 ; 8.584 ; 9.283 ; 9.242 ; +; SW[4] ; VGA_G[0] ; 8.652 ; 8.475 ; 9.234 ; 9.066 ; +; SW[4] ; VGA_G[1] ; 9.016 ; 8.875 ; 9.652 ; 9.511 ; +; SW[4] ; VGA_G[2] ; 8.756 ; 8.632 ; 9.342 ; 9.227 ; +; SW[4] ; VGA_G[3] ; 9.210 ; 9.093 ; 9.844 ; 9.730 ; +; SW[4] ; VGA_R[0] ; 8.916 ; 8.791 ; 9.563 ; 9.429 ; +; SW[4] ; VGA_R[1] ; 9.140 ; 9.076 ; 9.701 ; 9.628 ; +; SW[4] ; VGA_R[2] ; 8.626 ; 8.470 ; 9.215 ; 9.063 ; +; SW[4] ; VGA_R[3] ; 8.836 ; 8.685 ; 9.435 ; 9.279 ; +; SW[5] ; VGA_B[0] ; 8.150 ; 7.979 ; 8.767 ; 8.596 ; +; SW[5] ; VGA_B[1] ; 8.882 ; 8.754 ; 9.475 ; 9.347 ; +; SW[5] ; VGA_B[2] ; 8.247 ; 8.086 ; 8.912 ; 8.742 ; +; SW[5] ; VGA_B[3] ; 9.227 ; 9.142 ; 9.829 ; 9.788 ; +; SW[5] ; VGA_G[0] ; 8.549 ; 8.372 ; 9.098 ; 8.924 ; +; SW[5] ; VGA_G[1] ; 9.002 ; 8.861 ; 9.616 ; 9.475 ; +; SW[5] ; VGA_G[2] ; 8.653 ; 8.529 ; 9.203 ; 9.084 ; +; SW[5] ; VGA_G[3] ; 9.192 ; 9.078 ; 9.808 ; 9.694 ; +; SW[5] ; VGA_R[0] ; 8.583 ; 8.458 ; 9.256 ; 9.122 ; +; SW[5] ; VGA_R[1] ; 9.959 ; 9.909 ; 10.554 ; 10.517 ; +; SW[5] ; VGA_R[2] ; 8.412 ; 8.256 ; 9.035 ; 8.879 ; +; SW[5] ; VGA_R[3] ; 9.269 ; 9.113 ; 9.869 ; 9.713 ; ++------------+-------------+-------+-------+--------+--------+ + + ++------------------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+-------+-------+--------+--------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+--------+--------+ +; SW[4] ; VGA_B[0] ; 8.318 ; 8.157 ; 8.906 ; 8.740 ; +; SW[4] ; VGA_B[1] ; 7.917 ; 7.781 ; 8.472 ; 8.379 ; +; SW[4] ; VGA_B[2] ; 8.296 ; 8.135 ; 8.886 ; 8.725 ; +; SW[4] ; VGA_B[3] ; 7.775 ; 7.655 ; 8.329 ; 8.241 ; +; SW[4] ; VGA_G[0] ; 8.311 ; 8.144 ; 8.924 ; 8.748 ; +; SW[4] ; VGA_G[1] ; 8.317 ; 8.168 ; 8.884 ; 8.778 ; +; SW[4] ; VGA_G[2] ; 8.411 ; 8.294 ; 9.025 ; 8.899 ; +; SW[4] ; VGA_G[3] ; 8.009 ; 7.899 ; 8.621 ; 8.452 ; +; SW[4] ; VGA_R[0] ; 8.621 ; 8.496 ; 9.214 ; 9.089 ; +; SW[4] ; VGA_R[1] ; 8.479 ; 8.359 ; 9.031 ; 8.943 ; +; SW[4] ; VGA_R[2] ; 8.381 ; 8.235 ; 8.964 ; 8.813 ; +; SW[4] ; VGA_R[3] ; 8.287 ; 8.124 ; 8.846 ; 8.726 ; +; SW[5] ; VGA_B[0] ; 7.751 ; 7.574 ; 8.324 ; 8.190 ; +; SW[5] ; VGA_B[1] ; 8.626 ; 8.506 ; 9.174 ; 9.054 ; +; SW[5] ; VGA_B[2] ; 7.611 ; 7.449 ; 8.184 ; 8.052 ; +; SW[5] ; VGA_B[3] ; 8.857 ; 8.761 ; 9.438 ; 9.342 ; +; SW[5] ; VGA_G[0] ; 7.926 ; 7.758 ; 8.482 ; 8.344 ; +; SW[5] ; VGA_G[1] ; 8.684 ; 8.551 ; 9.273 ; 9.131 ; +; SW[5] ; VGA_G[2] ; 8.027 ; 7.909 ; 8.581 ; 8.493 ; +; SW[5] ; VGA_G[3] ; 8.836 ; 8.731 ; 9.457 ; 9.277 ; +; SW[5] ; VGA_R[0] ; 7.938 ; 7.812 ; 8.509 ; 8.413 ; +; SW[5] ; VGA_R[1] ; 9.562 ; 9.469 ; 10.169 ; 10.046 ; +; SW[5] ; VGA_R[2] ; 8.006 ; 7.844 ; 8.579 ; 8.460 ; +; SW[5] ; VGA_R[3] ; 8.997 ; 8.850 ; 9.552 ; 9.405 ; ++------------+-------------+-------+-------+--------+--------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Output Enable Times ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 3.156 ; 3.156 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 3.622 ; 3.622 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 3.156 ; 3.156 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 3.166 ; 3.166 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 3.325 ; 3.325 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 3.361 ; 3.361 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 3.156 ; 3.156 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 3.381 ; 3.381 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 3.342 ; 3.342 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 3.659 ; 3.659 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 3.659 ; 3.659 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 3.642 ; 3.642 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 3.649 ; 3.649 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 3.632 ; 3.632 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 3.642 ; 3.642 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 3.622 ; 3.622 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 3.361 ; 3.361 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Minimum Output Enable Times ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 2.448 ; 2.448 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.895 ; 2.895 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.448 ; 2.448 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.458 ; 2.458 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.610 ; 2.610 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.644 ; 2.644 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.448 ; 2.448 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.664 ; 2.664 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.626 ; 2.626 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.931 ; 2.931 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.931 ; 2.931 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.915 ; 2.915 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.921 ; 2.921 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.905 ; 2.905 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.915 ; 2.915 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.895 ; 2.895 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 2.644 ; 2.644 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Output Disable Times ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 3.089 ; 3.191 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 3.549 ; 3.651 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 3.089 ; 3.191 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 3.099 ; 3.201 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 3.246 ; 3.348 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 3.284 ; 3.386 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 3.089 ; 3.191 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 3.304 ; 3.406 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 3.275 ; 3.377 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 3.584 ; 3.686 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 3.584 ; 3.686 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 3.569 ; 3.671 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 3.574 ; 3.676 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 3.559 ; 3.661 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 3.569 ; 3.671 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 3.549 ; 3.651 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 3.284 ; 3.386 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Minimum Output Disable Times ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 2.482 ; 2.578 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.923 ; 3.019 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.482 ; 2.578 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.492 ; 2.588 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.632 ; 2.728 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.668 ; 2.764 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.482 ; 2.578 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.688 ; 2.784 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.660 ; 2.756 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.957 ; 3.053 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.957 ; 3.053 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.943 ; 3.039 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.947 ; 3.043 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.933 ; 3.029 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.943 ; 3.039 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.923 ; 3.019 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 2.668 ; 2.764 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ + + +---------------- +; MTBF Summary ; +---------------- +Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. +Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + +Number of Synchronizer Chains Found: 40 +Shortest Synchronizer Chain: 2 Registers +Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 +Worst Case Available Settling Time: 10.993 ns + +Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5 +Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9 + + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Synchronizer Summary ; ++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; Source Node ; Synchronization Node ; Worst-Case MTBF (Years) ; Typical MTBF (Years) ; Included in Design MTBF ; ++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; ++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ + + +Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 10.993 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; ; ; ; 6.819 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; ; ; ; 4.174 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.140 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; ; ; ; 7.252 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; ; ; ; 3.888 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.182 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; ; ; ; 7.251 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; ; ; ; 3.931 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.264 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; ; ; ; 6.820 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; ; ; ; 4.444 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.295 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; ; ; ; 7.105 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; ; ; ; 4.190 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.451 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; ; ; ; 7.248 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; ; ; ; 4.203 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.541 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; ; ; ; 7.253 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; ; ; ; 4.288 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.556 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; ; ; ; 7.251 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; ; ; ; 4.305 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.687 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; ; ; ; 7.249 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; ; ; ; 4.438 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.706 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; ; ; ; 7.252 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; ; ; ; 4.454 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.782 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; ; ; ; 7.105 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; ; ; ; 4.677 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.861 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; ; ; ; 7.106 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; ; ; ; 4.755 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.872 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; ; ; ; 6.647 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; ; ; ; 5.225 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.875 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; ; ; ; 7.250 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; ; ; ; 4.625 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.923 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; ; ; ; 7.105 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; ; ; ; 4.818 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.944 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; ; ; ; 7.174 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; ; ; ; 4.770 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.975 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; ; ; ; 6.900 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; ; ; ; 5.075 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.011 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; ; ; ; 7.251 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; ; ; ; 4.760 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.049 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; ; ; ; 7.106 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; ; ; ; 4.943 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.061 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; ; ; ; 7.106 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; ; ; ; 4.955 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.110 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; ; ; ; 7.267 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; ; ; ; 4.843 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.112 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; ; ; ; 6.989 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; ; ; ; 5.123 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.122 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; ; ; ; 6.901 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; ; ; ; 5.221 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.181 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; ; ; ; 7.121 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; ; ; ; 5.060 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.189 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; ; ; ; 7.106 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; ; ; ; 5.083 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.191 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; ; ; ; 7.118 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; ; ; ; 5.073 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.254 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; ; ; ; 6.900 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; ; ; ; 5.354 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.262 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; ; ; ; 6.995 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; ; ; ; 5.267 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.267 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; ; ; ; 7.123 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; ; ; ; 5.144 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.281 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; ; ; ; 6.992 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; ; ; ; 5.289 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.296 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; ; ; ; 7.148 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; ; ; ; 5.148 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.330 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; ; ; ; 7.108 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; ; ; ; 5.222 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.373 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; ; ; ; 6.970 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; ; ; ; 5.403 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.381 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; ; ; ; 7.122 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; ; ; ; 5.259 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.499 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; ; ; ; 7.105 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; ; ; ; 5.394 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.502 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; ; ; ; 7.104 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; ; ; ; 5.398 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.539 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; ; ; ; 7.140 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; ; ; ; 5.399 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.564 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; ; ; ; 7.250 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; ; ; ; 5.314 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.604 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; ; ; ; 6.900 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; ; ; ; 5.704 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.668 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; ; ; ; 6.969 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; ; ; ; 5.699 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + ++-------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Fmax Summary ; ++------------+-----------------+-----------------------------------------------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+-----------------------------------------------------+------+ +; 194.78 MHz ; 194.78 MHz ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; +; 215.47 MHz ; 215.47 MHz ; CLOCK_50 ; ; ++------------+-----------------+-----------------------------------------------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Setup Summary ; ++-----------------------------------------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+--------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.022 ; 0.000 ; +; CLOCK_50 ; 15.359 ; 0.000 ; ++-----------------------------------------------------+--------+---------------+ + + ++-----------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold Summary ; ++-----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+-------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.298 ; 0.000 ; +; CLOCK_50 ; 0.312 ; 0.000 ; ++-----------------------------------------------------+-------+---------------+ + + ++------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Recovery Summary ; ++-----------------------------------------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+--------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -0.828 ; -158.364 ; +; CLOCK_50 ; 14.667 ; 0.000 ; ++-----------------------------------------------------+--------+---------------+ + + ++-----------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Removal Summary ; ++-----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+-------+---------------+ +; CLOCK_50 ; 1.412 ; 0.000 ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.602 ; 0.000 ; ++-----------------------------------------------------+-------+---------------+ + + ++-----------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; ++-----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+-------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.739 ; 0.000 ; +; CLOCK_50 ; 9.562 ; 0.000 ; ++-----------------------------------------------------+-------+---------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; 0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.900 ; 2.093 ; +; 0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.900 ; 2.093 ; +; 0.077 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.210 ; 1.728 ; +; 0.077 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.210 ; 1.728 ; +; 0.077 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.210 ; 1.728 ; +; 0.077 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.210 ; 1.728 ; +; 0.077 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.210 ; 1.728 ; +; 0.077 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.210 ; 1.728 ; +; 0.077 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.210 ; 1.728 ; +; 0.077 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.210 ; 1.728 ; +; 0.077 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.210 ; 1.728 ; +; 0.077 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.210 ; 1.728 ; +; 0.077 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.210 ; 1.728 ; +; 0.077 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.210 ; 1.728 ; +; 0.077 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.210 ; 1.728 ; +; 0.077 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.210 ; 1.728 ; +; 0.077 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.210 ; 1.728 ; +; 0.083 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.899 ; 2.033 ; +; 0.083 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.899 ; 2.033 ; +; 0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.992 ; +; 0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.992 ; +; 0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.992 ; +; 0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.992 ; +; 0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.992 ; +; 0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.992 ; +; 0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.992 ; +; 0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.992 ; +; 0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.992 ; +; 0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.992 ; +; 0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.992 ; +; 0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.992 ; +; 0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.992 ; +; 0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.992 ; +; 0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.992 ; +; 0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.909 ; 1.963 ; +; 0.167 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.968 ; +; 0.167 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.968 ; +; 0.167 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.968 ; +; 0.167 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.968 ; +; 0.167 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.968 ; +; 0.167 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.968 ; +; 0.167 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.968 ; +; 0.167 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.968 ; +; 0.167 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.968 ; +; 0.167 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.968 ; +; 0.167 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.968 ; +; 0.167 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.968 ; +; 0.167 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.968 ; +; 0.167 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.968 ; +; 0.167 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.880 ; 1.968 ; +; 0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.903 ; 1.830 ; +; 0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.903 ; 1.830 ; +; 0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.903 ; 1.830 ; +; 0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.903 ; 1.830 ; +; 0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.903 ; 1.830 ; +; 0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.903 ; 1.830 ; +; 0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.903 ; 1.830 ; +; 0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.903 ; 1.830 ; +; 0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.903 ; 1.830 ; +; 0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.903 ; 1.830 ; +; 0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.903 ; 1.830 ; +; 0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.903 ; 1.830 ; +; 0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.903 ; 1.830 ; +; 0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.903 ; 1.830 ; +; 0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.903 ; 1.830 ; +; 0.340 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.895 ; 1.780 ; +; 0.340 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.895 ; 1.780 ; +; 0.340 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.895 ; 1.780 ; +; 0.350 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.879 ; 1.786 ; +; 0.350 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.879 ; 1.786 ; +; 0.350 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.879 ; 1.786 ; +; 0.350 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.879 ; 1.786 ; +; 0.350 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.879 ; 1.786 ; +; 0.350 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.879 ; 1.786 ; +; 0.350 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.879 ; 1.786 ; +; 0.399 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.870 ; 1.746 ; +; 0.399 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.870 ; 1.746 ; +; 0.399 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.870 ; 1.746 ; +; 0.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.908 ; 1.681 ; +; 0.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.908 ; 1.681 ; +; 0.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.908 ; 1.681 ; +; 2.866 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.239 ; 5.388 ; +; 2.866 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.239 ; 5.388 ; +; 2.877 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.090 ; 5.048 ; +; 2.877 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.090 ; 5.048 ; +; 2.895 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.090 ; 5.030 ; +; 2.895 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.090 ; 5.030 ; +; 2.913 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.240 ; 5.342 ; +; 2.913 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.240 ; 5.342 ; +; 2.916 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.269 ; 5.368 ; +; 2.928 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.269 ; 5.356 ; +; 2.930 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.089 ; 4.996 ; +; 2.930 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.089 ; 4.996 ; +; 2.938 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.089 ; 4.988 ; +; 2.938 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.089 ; 4.988 ; +; 2.942 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.089 ; 4.984 ; +; 2.942 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.089 ; 4.984 ; +; 2.950 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.230 ; 5.295 ; +; 2.977 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.088 ; 4.950 ; +; 2.977 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.088 ; 4.950 ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Setup: 'CLOCK_50' ; ++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.590 ; +; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.590 ; +; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.590 ; +; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.590 ; +; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.590 ; +; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.590 ; +; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.590 ; +; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.590 ; +; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.590 ; +; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.590 ; +; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.590 ; +; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.590 ; +; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.590 ; +; 15.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.581 ; +; 15.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.581 ; +; 15.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.581 ; +; 15.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.581 ; +; 15.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.581 ; +; 15.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.581 ; +; 15.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.581 ; +; 15.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.581 ; +; 15.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.581 ; +; 15.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.581 ; +; 15.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.581 ; +; 15.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.581 ; +; 15.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.581 ; +; 15.418 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.542 ; +; 15.418 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.542 ; +; 15.418 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.542 ; +; 15.418 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.542 ; +; 15.418 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.542 ; +; 15.418 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.542 ; +; 15.418 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.542 ; +; 15.418 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.542 ; +; 15.418 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.542 ; +; 15.418 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.542 ; +; 15.418 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.542 ; +; 15.418 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.542 ; +; 15.418 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.542 ; +; 15.418 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.542 ; +; 15.418 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.542 ; +; 15.418 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.542 ; +; 15.429 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.531 ; +; 15.429 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.531 ; +; 15.429 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.531 ; +; 15.429 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.531 ; +; 15.429 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.531 ; +; 15.429 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.531 ; +; 15.429 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.531 ; +; 15.429 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.531 ; +; 15.429 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.531 ; +; 15.429 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.531 ; +; 15.429 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.531 ; +; 15.429 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.531 ; +; 15.429 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.531 ; +; 15.429 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.531 ; +; 15.429 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.531 ; +; 15.429 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.055 ; 4.531 ; +; 15.448 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.501 ; +; 15.448 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.501 ; +; 15.448 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.501 ; +; 15.448 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.501 ; +; 15.448 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.501 ; +; 15.448 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.501 ; +; 15.448 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.501 ; +; 15.448 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.501 ; +; 15.448 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.501 ; +; 15.448 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.501 ; +; 15.448 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.501 ; +; 15.448 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.501 ; +; 15.448 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.066 ; 4.501 ; +; 15.449 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.512 ; +; 15.449 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.512 ; +; 15.449 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.512 ; +; 15.449 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.512 ; +; 15.449 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.512 ; +; 15.449 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.512 ; +; 15.449 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.512 ; +; 15.449 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.512 ; +; 15.449 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.512 ; +; 15.449 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.512 ; +; 15.449 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.512 ; +; 15.449 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.512 ; +; 15.449 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.512 ; +; 15.449 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.512 ; +; 15.449 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.512 ; +; 15.460 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.501 ; +; 15.460 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.501 ; +; 15.460 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.501 ; +; 15.460 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.501 ; +; 15.460 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.501 ; +; 15.460 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.501 ; +; 15.460 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.501 ; +; 15.460 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.501 ; +; 15.460 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.501 ; +; 15.460 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.501 ; +; 15.460 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.501 ; +; 15.460 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.501 ; +; 15.460 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.501 ; +; 15.460 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.054 ; 4.501 ; ++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; 0.298 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 0.511 ; +; 0.298 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 0.511 ; +; 0.299 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.511 ; +; 0.299 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.511 ; +; 0.299 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.511 ; +; 0.299 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.511 ; +; 0.299 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.511 ; +; 0.299 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.511 ; +; 0.299 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 0.511 ; +; 0.302 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.386 ; 0.832 ; +; 0.311 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.054 ; 0.511 ; +; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.054 ; 0.511 ; +; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.054 ; 0.511 ; +; 0.317 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.529 ; +; 0.319 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.519 ; +; 0.320 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.519 ; +; 0.320 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.519 ; +; 0.325 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.537 ; +; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.538 ; +; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.538 ; +; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.539 ; +; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.539 ; +; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.539 ; +; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.539 ; +; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.539 ; +; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.539 ; +; 0.328 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.540 ; +; 0.330 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.529 ; +; 0.331 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.530 ; +; 0.331 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.338 ; 0.838 ; +; 0.333 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.545 ; +; 0.333 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.545 ; +; 0.335 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.334 ; 0.838 ; +; 0.335 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.547 ; +; 0.335 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.338 ; 0.842 ; +; 0.336 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 0.548 ; +; 0.337 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.536 ; +; 0.338 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.538 ; +; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.538 ; +; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[6] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.538 ; +; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.538 ; +; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REFRESH ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_refresh ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.538 ; +; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_done ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.539 ; +; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.539 ; +; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.538 ; +; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.539 ; +; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.539 ; +; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.539 ; +; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[15] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.539 ; +; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[16] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[8] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.539 ; +; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[17] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.539 ; +; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.539 ; +; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|RAS_N ; DE0_D5M:inst|Sdram_Control_4Port:u7|RAS_N ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.539 ; +; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|BA[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.539 ; +; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.386 ; 0.870 ; +; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_shift[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.539 ; +; 0.342 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.541 ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold: 'CLOCK_50' ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 0.312 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.511 ; +; 0.313 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.511 ; +; 0.320 ; DE0_D5M:inst|Reset_Delay:u2|Cont[0] ; DE0_D5M:inst|Reset_Delay:u2|Cont[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.519 ; +; 0.320 ; ps2:inst6|clk_div[0] ; ps2:inst6|clk_div[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.519 ; +; 0.333 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 0.511 ; +; 0.339 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.538 ; +; 0.340 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.539 ; +; 0.341 ; DE0_D5M:inst|rClk[0] ; DE0_D5M:inst|rClk[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 0.519 ; +; 0.347 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.545 ; +; 0.347 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.546 ; +; 0.386 ; ps2:inst6|clk_div[8] ; ps2:inst6|clk_div[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 0.564 ; +; 0.470 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.669 ; +; 0.495 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.694 ; +; 0.495 ; ps2:inst6|clk_div[4] ; ps2:inst6|clk_div[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.694 ; +; 0.496 ; ps2:inst6|clk_div[3] ; ps2:inst6|clk_div[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.695 ; +; 0.497 ; ps2:inst6|clk_div[2] ; ps2:inst6|clk_div[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.696 ; +; 0.498 ; ps2:inst6|clk_div[6] ; ps2:inst6|clk_div[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.697 ; +; 0.499 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.698 ; +; 0.499 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.698 ; +; 0.499 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.698 ; +; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.699 ; +; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.699 ; +; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.699 ; +; 0.500 ; ps2:inst6|clk_div[7] ; ps2:inst6|clk_div[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.699 ; +; 0.500 ; ps2:inst6|clk_div[5] ; ps2:inst6|clk_div[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.699 ; +; 0.501 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.700 ; +; 0.501 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.700 ; +; 0.501 ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.700 ; +; 0.501 ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.700 ; +; 0.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.701 ; +; 0.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.701 ; +; 0.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.701 ; +; 0.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.701 ; +; 0.502 ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.701 ; +; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.702 ; +; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.702 ; +; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.702 ; +; 0.504 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.703 ; +; 0.504 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.703 ; +; 0.504 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.703 ; +; 0.504 ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.703 ; +; 0.505 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.704 ; +; 0.505 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.704 ; +; 0.506 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.705 ; +; 0.508 ; ps2:inst6|clk_div[1] ; ps2:inst6|clk_div[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.707 ; +; 0.508 ; ps2:inst6|clk_div[0] ; ps2:inst6|clk_div[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.707 ; +; 0.511 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.710 ; +; 0.511 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.710 ; +; 0.511 ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.710 ; +; 0.511 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.710 ; +; 0.511 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.710 ; +; 0.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.711 ; +; 0.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.711 ; +; 0.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.711 ; +; 0.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.711 ; +; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.711 ; +; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.711 ; +; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[14] ; DE0_D5M:inst|Reset_Delay:u2|Cont[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.711 ; +; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.711 ; +; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.711 ; +; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.711 ; +; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.711 ; +; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.711 ; +; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.711 ; +; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.712 ; +; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.712 ; +; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.712 ; +; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.712 ; +; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.712 ; +; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.712 ; +; 0.514 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.713 ; +; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.713 ; +; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.713 ; +; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.713 ; +; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.713 ; +; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.713 ; +; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.713 ; +; 0.515 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.714 ; +; 0.515 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.714 ; +; 0.515 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.714 ; +; 0.515 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.714 ; +; 0.515 ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.714 ; +; 0.515 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.714 ; +; 0.516 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.715 ; +; 0.516 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.715 ; +; 0.516 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.715 ; +; 0.516 ; DE0_D5M:inst|Reset_Delay:u2|Cont[9] ; DE0_D5M:inst|Reset_Delay:u2|Cont[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.715 ; +; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.716 ; +; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.716 ; +; 0.517 ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.716 ; +; 0.517 ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.716 ; +; 0.520 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.055 ; 0.719 ; +; 0.526 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.724 ; +; 0.526 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.724 ; +; 0.530 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.728 ; +; 0.530 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.728 ; +; 0.531 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.729 ; +; 0.532 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.730 ; +; 0.639 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 0.837 ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; -0.828 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.992 ; 2.794 ; +; -0.828 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.992 ; 2.794 ; +; -0.828 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.992 ; 2.794 ; +; -0.828 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.992 ; 2.794 ; +; -0.828 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.992 ; 2.794 ; +; -0.828 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.992 ; 2.794 ; +; -0.828 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.992 ; 2.794 ; +; -0.828 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.992 ; 2.794 ; +; -0.828 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.992 ; 2.794 ; +; -0.828 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.992 ; 2.794 ; +; -0.828 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.992 ; 2.794 ; +; -0.828 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.992 ; 2.794 ; +; -0.828 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.992 ; 2.794 ; +; -0.828 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.992 ; 2.794 ; +; -0.828 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.992 ; 2.794 ; +; -0.828 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.992 ; 2.794 ; +; -0.815 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.984 ; 2.789 ; +; -0.815 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.984 ; 2.789 ; +; -0.815 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.984 ; 2.789 ; +; -0.815 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.984 ; 2.789 ; +; -0.815 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.984 ; 2.789 ; +; -0.815 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.984 ; 2.789 ; +; -0.815 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.984 ; 2.789 ; +; -0.815 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.984 ; 2.789 ; +; -0.815 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.984 ; 2.789 ; +; -0.815 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.984 ; 2.789 ; +; -0.815 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.984 ; 2.789 ; +; -0.815 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.984 ; 2.789 ; +; -0.815 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.984 ; 2.789 ; +; -0.815 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.984 ; 2.789 ; +; -0.815 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.984 ; 2.789 ; +; -0.815 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.984 ; 2.789 ; +; -0.784 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.990 ; 2.834 ; +; -0.771 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.982 ; 2.829 ; +; -0.683 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.206 ; 2.492 ; +; -0.683 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.206 ; 2.492 ; +; -0.683 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.206 ; 2.492 ; +; -0.683 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.206 ; 2.492 ; +; -0.683 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.206 ; 2.492 ; +; -0.683 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.206 ; 2.492 ; +; -0.682 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.206 ; 2.491 ; +; -0.682 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.206 ; 2.491 ; +; -0.682 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.206 ; 2.491 ; +; -0.682 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.206 ; 2.491 ; +; -0.682 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.206 ; 2.491 ; +; -0.682 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.206 ; 2.491 ; +; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.213 ; 2.476 ; +; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.213 ; 2.476 ; +; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.215 ; 2.474 ; +; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.215 ; 2.474 ; +; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.215 ; 2.474 ; +; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.215 ; 2.474 ; +; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.215 ; 2.474 ; +; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.215 ; 2.474 ; +; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.215 ; 2.474 ; +; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.215 ; 2.474 ; +; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.215 ; 2.474 ; +; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.215 ; 2.474 ; +; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.215 ; 2.474 ; +; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.213 ; 2.476 ; +; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.213 ; 2.476 ; +; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.213 ; 2.476 ; +; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.213 ; 2.476 ; +; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.213 ; 2.476 ; +; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.213 ; 2.476 ; +; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.213 ; 2.476 ; +; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.213 ; 2.476 ; +; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.213 ; 2.476 ; +; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.213 ; 2.476 ; +; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.213 ; 2.476 ; +; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.213 ; 2.476 ; +; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.213 ; 2.476 ; +; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.213 ; 2.476 ; +; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.213 ; 2.476 ; +; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.213 ; 2.476 ; +; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.215 ; 2.474 ; +; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.213 ; 2.476 ; +; -0.673 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.215 ; 2.473 ; +; -0.673 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.215 ; 2.473 ; +; -0.673 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.215 ; 2.473 ; +; -0.673 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.215 ; 2.473 ; +; -0.673 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.215 ; 2.473 ; +; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.200 ; 2.478 ; +; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.200 ; 2.478 ; +; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.200 ; 2.478 ; +; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.200 ; 2.478 ; +; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.200 ; 2.478 ; +; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.200 ; 2.478 ; +; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.200 ; 2.478 ; +; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.200 ; 2.478 ; +; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.200 ; 2.478 ; +; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.201 ; 2.477 ; +; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.200 ; 2.478 ; +; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.201 ; 2.477 ; +; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.200 ; 2.478 ; +; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.201 ; 2.477 ; +; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.200 ; 2.478 ; +; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.201 ; 2.477 ; +; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.200 ; 2.478 ; +; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -2.201 ; 2.477 ; ++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Recovery: 'CLOCK_50' ; ++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 14.667 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.700 ; 4.648 ; +; 14.676 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.700 ; 4.639 ; +; 14.756 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.700 ; 4.559 ; +; 14.800 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.699 ; 4.516 ; +; 14.875 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.700 ; 4.440 ; +; 14.926 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.699 ; 4.390 ; +; 14.928 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.699 ; 4.388 ; +; 14.935 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.699 ; 4.381 ; +; 15.006 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.699 ; 4.310 ; +; 15.013 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.699 ; 4.303 ; +; 15.134 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.699 ; 4.182 ; +; 15.136 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.699 ; 4.180 ; +; 15.142 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.699 ; 4.174 ; +; 15.143 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.699 ; 4.173 ; +; 15.223 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.699 ; 4.093 ; +; 15.336 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.700 ; 3.979 ; +; 15.349 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.699 ; 3.967 ; +; 15.462 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.700 ; 3.853 ; +; 15.554 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.700 ; 3.761 ; +; 15.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.402 ; +; 15.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.402 ; +; 15.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.402 ; +; 15.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.402 ; +; 15.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.402 ; +; 15.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.402 ; +; 15.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.402 ; +; 15.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.402 ; +; 15.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.402 ; +; 15.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.402 ; +; 15.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.402 ; +; 15.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.402 ; +; 15.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.402 ; +; 15.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.402 ; +; 15.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.402 ; +; 15.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.402 ; +; 15.565 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.393 ; +; 15.565 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.393 ; +; 15.565 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.393 ; +; 15.565 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.393 ; +; 15.565 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.393 ; +; 15.565 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.393 ; +; 15.565 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.393 ; +; 15.565 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.393 ; +; 15.565 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.393 ; +; 15.565 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.393 ; +; 15.565 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.393 ; +; 15.565 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.393 ; +; 15.565 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.393 ; +; 15.565 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.393 ; +; 15.565 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.393 ; +; 15.565 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.393 ; +; 15.583 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.700 ; 3.732 ; +; 15.592 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.700 ; 3.723 ; +; 15.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.313 ; +; 15.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.313 ; +; 15.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.313 ; +; 15.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.313 ; +; 15.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.313 ; +; 15.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.313 ; +; 15.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.313 ; +; 15.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.313 ; +; 15.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.313 ; +; 15.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.313 ; +; 15.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.313 ; +; 15.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.313 ; +; 15.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.313 ; +; 15.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.313 ; +; 15.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.313 ; +; 15.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.313 ; +; 15.671 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.700 ; 3.644 ; +; 15.674 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.700 ; 3.641 ; +; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.056 ; 4.270 ; +; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.056 ; 4.270 ; +; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.056 ; 4.270 ; +; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.056 ; 4.270 ; +; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.056 ; 4.270 ; +; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.056 ; 4.270 ; +; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.056 ; 4.270 ; +; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.056 ; 4.270 ; +; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.056 ; 4.270 ; +; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.056 ; 4.270 ; +; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.056 ; 4.270 ; +; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.056 ; 4.270 ; +; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.056 ; 4.270 ; +; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.056 ; 4.270 ; +; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.056 ; 4.270 ; +; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.056 ; 4.270 ; +; 15.772 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.186 ; +; 15.772 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.186 ; +; 15.772 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.186 ; +; 15.772 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.186 ; +; 15.772 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.186 ; +; 15.772 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.186 ; +; 15.772 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.186 ; +; 15.772 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.186 ; +; 15.772 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.186 ; +; 15.772 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.186 ; +; 15.772 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.186 ; +; 15.772 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.186 ; +; 15.772 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.057 ; 4.186 ; ++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Removal: 'CLOCK_50' ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 1.412 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.610 ; +; 1.412 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.610 ; +; 1.412 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.610 ; +; 1.412 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.610 ; +; 1.412 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.610 ; +; 1.412 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.610 ; +; 1.412 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.610 ; +; 1.412 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.610 ; +; 1.412 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.610 ; +; 1.412 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.610 ; +; 1.412 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.610 ; +; 1.412 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.610 ; +; 1.412 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.610 ; +; 1.412 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.610 ; +; 1.412 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.610 ; +; 1.412 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.610 ; +; 1.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.779 ; +; 1.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.779 ; +; 1.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.779 ; +; 1.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.779 ; +; 1.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.779 ; +; 1.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.779 ; +; 1.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.779 ; +; 1.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.779 ; +; 1.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.779 ; +; 1.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.779 ; +; 1.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.779 ; +; 1.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.779 ; +; 1.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.779 ; +; 1.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.779 ; +; 1.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.779 ; +; 1.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 1.779 ; +; 2.000 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.065 ; 2.209 ; +; 2.000 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.065 ; 2.209 ; +; 2.000 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.065 ; 2.209 ; +; 2.000 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.065 ; 2.209 ; +; 2.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.065 ; 2.231 ; +; 2.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.065 ; 2.231 ; +; 2.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.065 ; 2.231 ; +; 2.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.065 ; 2.231 ; +; 2.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.065 ; 2.231 ; +; 2.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.065 ; 2.231 ; +; 2.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.065 ; 2.231 ; +; 2.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.065 ; 2.231 ; +; 2.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.065 ; 2.231 ; +; 2.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.065 ; 2.231 ; +; 2.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.065 ; 2.231 ; +; 2.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.065 ; 2.231 ; +; 2.071 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.066 ; 2.281 ; +; 2.071 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.066 ; 2.281 ; +; 2.071 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.066 ; 2.281 ; +; 2.071 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.066 ; 2.281 ; +; 2.071 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.066 ; 2.281 ; +; 2.071 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.066 ; 2.281 ; +; 2.071 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.066 ; 2.281 ; +; 2.071 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.066 ; 2.281 ; +; 2.071 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.066 ; 2.281 ; +; 2.071 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.066 ; 2.281 ; +; 2.071 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.066 ; 2.281 ; +; 2.071 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.066 ; 2.281 ; +; 2.071 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.066 ; 2.281 ; +; 2.286 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 2.484 ; +; 2.286 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 2.484 ; +; 2.286 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 2.484 ; +; 2.286 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 2.484 ; +; 2.286 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 2.484 ; +; 2.286 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 2.484 ; +; 2.286 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 2.484 ; +; 2.286 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 2.484 ; +; 2.286 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 2.484 ; +; 2.286 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 2.484 ; +; 2.286 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 2.484 ; +; 2.286 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 2.484 ; +; 2.286 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 2.484 ; +; 2.286 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.054 ; 2.484 ; +; 2.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 0.000 ; -0.578 ; 1.865 ; +; 2.450 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 0.000 ; -0.578 ; 2.016 ; +; 2.703 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.911 ; +; 2.703 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.911 ; +; 2.703 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.911 ; +; 2.703 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.911 ; +; 2.703 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.911 ; +; 2.703 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.911 ; +; 2.703 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.911 ; +; 2.703 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.911 ; +; 2.703 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.911 ; +; 2.703 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.911 ; +; 2.703 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.911 ; +; 2.703 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.911 ; +; 2.703 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.911 ; +; 2.703 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.911 ; +; 2.703 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.911 ; +; 2.703 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.064 ; 2.911 ; +; 2.834 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.053 ; 3.031 ; +; 2.834 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.053 ; 3.031 ; +; 2.834 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.053 ; 3.031 ; +; 2.834 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.053 ; 3.031 ; +; 2.834 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.053 ; 3.031 ; +; 2.834 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.053 ; 3.031 ; +; 2.834 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.053 ; 3.031 ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; 3.602 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.427 ; 2.319 ; +; 3.602 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.427 ; 2.319 ; +; 3.616 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.433 ; 2.327 ; +; 3.616 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.433 ; 2.327 ; +; 3.616 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.433 ; 2.327 ; +; 3.616 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.433 ; 2.327 ; +; 3.616 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.433 ; 2.327 ; +; 3.616 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.433 ; 2.327 ; +; 3.616 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.433 ; 2.327 ; +; 3.616 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.433 ; 2.327 ; +; 3.616 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.433 ; 2.327 ; +; 3.616 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.433 ; 2.327 ; +; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.443 ; 2.325 ; +; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.443 ; 2.325 ; +; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.443 ; 2.325 ; +; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.443 ; 2.325 ; +; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.443 ; 2.325 ; +; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.447 ; 2.321 ; +; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.447 ; 2.321 ; +; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.447 ; 2.321 ; +; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.447 ; 2.321 ; +; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.447 ; 2.321 ; +; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.447 ; 2.321 ; +; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.447 ; 2.321 ; +; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.441 ; 2.327 ; +; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.443 ; 2.325 ; +; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.441 ; 2.327 ; +; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.441 ; 2.327 ; +; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.441 ; 2.327 ; +; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.441 ; 2.327 ; +; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.441 ; 2.327 ; +; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.441 ; 2.327 ; +; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.441 ; 2.327 ; +; 3.625 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.323 ; +; 3.625 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.323 ; +; 3.625 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.323 ; +; 3.625 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.323 ; +; 3.625 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.323 ; +; 3.625 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.323 ; +; 3.625 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.323 ; +; 3.625 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.323 ; +; 3.625 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.323 ; +; 3.625 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.446 ; 2.323 ; +; 3.629 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.321 ; +; 3.629 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.321 ; +; 3.629 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.321 ; +; 3.629 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.321 ; +; 3.629 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.321 ; +; 3.629 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.321 ; +; 3.629 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.321 ; +; 3.629 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.321 ; +; 3.629 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.321 ; +; 3.629 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.321 ; +; 3.629 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.321 ; +; 3.629 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.321 ; +; 3.629 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.321 ; +; 3.636 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.457 ; 2.323 ; +; 3.636 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.457 ; 2.323 ; +; 3.636 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.457 ; 2.323 ; +; 3.636 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.457 ; 2.323 ; +; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.442 ; 2.340 ; +; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.442 ; 2.340 ; +; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.442 ; 2.340 ; +; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.442 ; 2.340 ; +; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.442 ; 2.340 ; +; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.442 ; 2.340 ; +; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.442 ; 2.340 ; +; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.442 ; 2.340 ; +; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.442 ; 2.340 ; +; 3.642 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.459 ; 2.327 ; +; 3.642 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.459 ; 2.327 ; +; 3.642 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.459 ; 2.327 ; +; 3.642 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.459 ; 2.327 ; +; 3.642 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.459 ; 2.327 ; +; 3.644 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.447 ; 2.341 ; +; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.338 ; +; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.453 ; 2.337 ; +; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.453 ; 2.337 ; +; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.338 ; +; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.338 ; +; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.338 ; +; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.453 ; 2.337 ; +; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.453 ; 2.337 ; +; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.338 ; +; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.338 ; +; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.338 ; +; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.338 ; +; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.453 ; 2.337 ; +; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.453 ; 2.337 ; +; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.453 ; 2.337 ; +; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.338 ; +; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.338 ; +; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.338 ; +; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.453 ; 2.337 ; +; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.453 ; 2.337 ; +; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.452 ; 2.338 ; +; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.453 ; 2.337 ; +; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.453 ; 2.337 ; +; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.453 ; 2.337 ; +; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.453 ; 2.337 ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; 3.739 ; 3.955 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; +; 3.739 ; 3.955 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; +; 3.739 ; 3.955 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; +; 3.739 ; 3.955 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; +; 3.739 ; 3.955 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; +; 3.739 ; 3.955 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; +; 3.739 ; 3.955 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; +; 3.739 ; 3.955 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; +; 3.740 ; 3.970 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; +; 3.740 ; 3.970 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_we_reg ; +; 3.740 ; 3.956 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; +; 3.740 ; 3.956 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; +; 3.740 ; 3.956 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; +; 3.740 ; 3.956 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; +; 3.740 ; 3.956 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; +; 3.740 ; 3.956 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; +; 3.740 ; 3.956 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; +; 3.740 ; 3.956 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; +; 3.741 ; 3.957 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; +; 3.741 ; 3.957 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; +; 3.741 ; 3.957 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; +; 3.741 ; 3.957 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; +; 3.741 ; 3.957 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; +; 3.741 ; 3.957 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; +; 3.741 ; 3.957 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; +; 3.741 ; 3.971 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; +; 3.741 ; 3.971 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_we_reg ; +; 3.741 ; 3.957 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15] ; +; 3.741 ; 3.957 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19] ; +; 3.741 ; 3.957 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20] ; +; 3.741 ; 3.957 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21] ; +; 3.742 ; 3.972 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0 ; +; 3.743 ; 3.959 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; +; 3.743 ; 3.959 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; +; 3.743 ; 3.959 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; +; 3.743 ; 3.959 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; +; 3.743 ; 3.959 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; +; 3.743 ; 3.959 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; +; 3.743 ; 3.973 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0 ; +; 3.743 ; 3.959 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; +; 3.743 ; 3.959 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; +; 3.743 ; 3.959 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; +; 3.743 ; 3.959 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; +; 3.743 ; 3.959 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[3] ; +; 3.743 ; 3.959 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[4] ; +; 3.744 ; 3.960 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4] ; +; 3.744 ; 3.960 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5] ; +; 3.744 ; 3.960 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6] ; +; 3.744 ; 3.960 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7] ; +; 3.744 ; 3.960 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9] ; +; 3.744 ; 3.960 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; +; 3.744 ; 3.960 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; +; 3.744 ; 3.960 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; +; 3.744 ; 3.960 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; +; 3.744 ; 3.960 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; +; 3.744 ; 3.960 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; +; 3.744 ; 3.960 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; +; 3.744 ; 3.960 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16] ; +; 3.744 ; 3.960 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17] ; +; 3.744 ; 3.960 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[1] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8] ; +; 3.745 ; 3.961 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9 ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1] ; +; 3.749 ; 3.965 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR ; +; 3.750 ; 3.966 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0] ; +; 3.750 ; 3.966 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[1] ; +; 3.750 ; 3.966 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[3] ; +; 3.750 ; 3.966 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[4] ; +; 3.750 ; 3.966 ; 0.216 ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[8] ; +; 3.750 ; 3.980 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; +; 3.750 ; 3.980 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; +; 3.750 ; 3.980 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; +; 3.750 ; 3.980 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; ++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' ; ++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+ +; 9.562 ; 9.746 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; +; 9.562 ; 9.746 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|rClk[0] ; +; 9.562 ; 9.746 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[8] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[14] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[1] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[9] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|oRST_1 ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[0] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[1] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[2] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[3] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[4] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[5] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[6] ; +; 9.588 ; 9.772 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[7] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[0] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; +; 9.589 ; 9.773 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; +; 9.590 ; 9.774 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; ++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Setup Times ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; SW[*] ; CLOCK_50 ; 3.692 ; 4.270 ; Rise ; CLOCK_50 ; +; SW[0] ; CLOCK_50 ; 3.692 ; 4.270 ; Rise ; CLOCK_50 ; +; SW[1] ; CLOCK_50 ; 3.554 ; 4.069 ; Rise ; CLOCK_50 ; +; DRAM_DQ[*] ; CLOCK_50 ; 3.612 ; 4.078 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 3.418 ; 3.906 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 3.162 ; 3.645 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 3.288 ; 3.732 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 3.311 ; 3.818 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 3.612 ; 4.078 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 3.144 ; 3.579 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 3.414 ; 3.881 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 3.143 ; 3.582 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 3.168 ; 3.602 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 3.130 ; 3.608 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 3.169 ; 3.610 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 3.169 ; 3.611 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 3.313 ; 3.766 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 3.165 ; 3.601 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 3.348 ; 3.793 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------+ +; Hold Times ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ +; SW[*] ; CLOCK_50 ; -1.802 ; -2.295 ; Rise ; CLOCK_50 ; +; SW[0] ; CLOCK_50 ; -1.802 ; -2.295 ; Rise ; CLOCK_50 ; +; SW[1] ; CLOCK_50 ; -1.816 ; -2.303 ; Rise ; CLOCK_50 ; +; DRAM_DQ[*] ; CLOCK_50 ; -2.507 ; -2.968 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; -2.810 ; -3.283 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; -2.540 ; -3.008 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; -2.696 ; -3.131 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; -2.694 ; -3.191 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; -2.972 ; -3.424 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; -2.546 ; -2.968 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; -2.807 ; -3.260 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; -2.544 ; -2.970 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; -2.570 ; -2.991 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; -2.507 ; -2.970 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; -2.571 ; -2.999 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; -2.571 ; -3.000 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; -2.722 ; -3.166 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; -2.567 ; -2.990 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; -2.744 ; -3.175 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------+ +; Clock to Output Times ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; GPIO_1[*] ; CLOCK_50 ; 6.098 ; 5.915 ; Rise ; CLOCK_50 ; +; GPIO_1[14] ; CLOCK_50 ; 5.946 ; 5.878 ; Rise ; CLOCK_50 ; +; GPIO_1[20] ; CLOCK_50 ; 6.098 ; 5.915 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[*] ; CLOCK_50 ; 5.416 ; 5.365 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[0] ; CLOCK_50 ; 5.416 ; 5.365 ; Rise ; CLOCK_50 ; +; VGA_CLK ; CLOCK_50 ; 5.228 ; 5.321 ; Rise ; CLOCK_50 ; +; DRAM_ADDR[*] ; CLOCK_50 ; 3.434 ; 3.272 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[0] ; CLOCK_50 ; 3.430 ; 3.268 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[1] ; CLOCK_50 ; 3.434 ; 3.272 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[2] ; CLOCK_50 ; 3.410 ; 3.255 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[3] ; CLOCK_50 ; 3.410 ; 3.256 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[4] ; CLOCK_50 ; 3.228 ; 3.089 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[5] ; CLOCK_50 ; 3.207 ; 3.075 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[6] ; CLOCK_50 ; 3.040 ; 2.920 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[7] ; CLOCK_50 ; 3.050 ; 2.930 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[8] ; CLOCK_50 ; 3.042 ; 2.918 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[9] ; CLOCK_50 ; 3.035 ; 2.919 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[10] ; CLOCK_50 ; 3.278 ; 3.144 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[11] ; CLOCK_50 ; 3.026 ; 2.912 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_0 ; CLOCK_50 ; 3.104 ; 3.009 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_1 ; CLOCK_50 ; 3.264 ; 3.154 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CAS_N ; CLOCK_50 ; 3.210 ; 3.074 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CS_N ; CLOCK_50 ; 3.572 ; 3.481 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[*] ; CLOCK_50 ; 7.279 ; 6.943 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 5.621 ; 5.416 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 5.638 ; 5.572 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 5.364 ; 5.227 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 7.279 ; 6.943 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 5.466 ; 5.343 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 5.649 ; 5.523 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 5.615 ; 5.397 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 5.565 ; 5.460 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 5.504 ; 5.380 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 5.559 ; 5.455 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 5.684 ; 5.550 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 5.733 ; 5.551 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 5.769 ; 5.642 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 5.749 ; 5.623 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 5.620 ; 5.420 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 5.587 ; 5.458 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_LDQM ; CLOCK_50 ; 3.456 ; 3.298 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_RAS_N ; CLOCK_50 ; 3.401 ; 3.247 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_UDQM ; CLOCK_50 ; 3.348 ; 3.232 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 5.256 ; 4.904 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CLK ; CLOCK_50 ; -0.448 ; ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; +; DRAM_CLK ; CLOCK_50 ; ; -0.595 ; Fall ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; GPIO_1[*] ; CLOCK_50 ; 5.810 ; 5.740 ; Rise ; CLOCK_50 ; +; GPIO_1[14] ; CLOCK_50 ; 5.810 ; 5.740 ; Rise ; CLOCK_50 ; +; GPIO_1[20] ; CLOCK_50 ; 5.957 ; 5.775 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[*] ; CLOCK_50 ; 5.301 ; 5.248 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[0] ; CLOCK_50 ; 5.301 ; 5.248 ; Rise ; CLOCK_50 ; +; VGA_CLK ; CLOCK_50 ; 5.116 ; 5.210 ; Rise ; CLOCK_50 ; +; DRAM_ADDR[*] ; CLOCK_50 ; 2.656 ; 2.540 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[0] ; CLOCK_50 ; 3.043 ; 2.882 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[1] ; CLOCK_50 ; 3.047 ; 2.888 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[2] ; CLOCK_50 ; 3.025 ; 2.871 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[3] ; CLOCK_50 ; 3.024 ; 2.871 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[4] ; CLOCK_50 ; 2.850 ; 2.712 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[5] ; CLOCK_50 ; 2.829 ; 2.697 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[6] ; CLOCK_50 ; 2.669 ; 2.549 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[7] ; CLOCK_50 ; 2.679 ; 2.559 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[8] ; CLOCK_50 ; 2.670 ; 2.546 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[9] ; CLOCK_50 ; 2.665 ; 2.548 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[10] ; CLOCK_50 ; 2.898 ; 2.765 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[11] ; CLOCK_50 ; 2.656 ; 2.540 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_0 ; CLOCK_50 ; 2.730 ; 2.635 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_1 ; CLOCK_50 ; 2.884 ; 2.774 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CAS_N ; CLOCK_50 ; 2.831 ; 2.696 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CS_N ; CLOCK_50 ; 3.178 ; 3.085 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[*] ; CLOCK_50 ; 3.594 ; 3.423 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 3.594 ; 3.423 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 4.355 ; 4.265 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 4.040 ; 3.912 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 5.925 ; 5.573 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 4.109 ; 3.971 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 4.238 ; 4.134 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 4.091 ; 3.943 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 4.260 ; 4.135 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 3.912 ; 3.768 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 3.950 ; 3.822 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 4.069 ; 3.911 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 3.961 ; 3.827 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 4.359 ; 4.203 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 4.146 ; 4.005 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 3.853 ; 3.683 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 3.971 ; 3.837 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_LDQM ; CLOCK_50 ; 3.067 ; 2.911 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_RAS_N ; CLOCK_50 ; 3.015 ; 2.862 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_UDQM ; CLOCK_50 ; 2.964 ; 2.848 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 4.876 ; 4.525 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CLK ; CLOCK_50 ; -0.777 ; ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; +; DRAM_CLK ; CLOCK_50 ; ; -0.922 ; Fall ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; SW[4] ; VGA_B[0] ; 7.976 ; 7.791 ; 8.504 ; 8.311 ; +; SW[4] ; VGA_B[1] ; 7.840 ; 7.650 ; 8.336 ; 8.138 ; +; SW[4] ; VGA_B[2] ; 7.955 ; 7.759 ; 8.484 ; 8.280 ; +; SW[4] ; VGA_B[3] ; 8.033 ; 7.902 ; 8.552 ; 8.463 ; +; SW[4] ; VGA_G[0] ; 8.023 ; 7.815 ; 8.508 ; 8.308 ; +; SW[4] ; VGA_G[1] ; 8.353 ; 8.150 ; 8.874 ; 8.671 ; +; SW[4] ; VGA_G[2] ; 8.110 ; 7.933 ; 8.593 ; 8.424 ; +; SW[4] ; VGA_G[3] ; 8.539 ; 8.342 ; 9.042 ; 8.865 ; +; SW[4] ; VGA_R[0] ; 8.270 ; 8.075 ; 8.800 ; 8.597 ; +; SW[4] ; VGA_R[1] ; 8.480 ; 8.328 ; 8.958 ; 8.798 ; +; SW[4] ; VGA_R[2] ; 7.996 ; 7.803 ; 8.491 ; 8.302 ; +; SW[4] ; VGA_R[3] ; 8.201 ; 8.016 ; 8.701 ; 8.508 ; +; SW[5] ; VGA_B[0] ; 7.569 ; 7.382 ; 8.078 ; 7.885 ; +; SW[5] ; VGA_B[1] ; 8.249 ; 8.057 ; 8.735 ; 8.537 ; +; SW[5] ; VGA_B[2] ; 7.658 ; 7.462 ; 8.200 ; 7.996 ; +; SW[5] ; VGA_B[3] ; 8.565 ; 8.428 ; 9.045 ; 8.956 ; +; SW[5] ; VGA_G[0] ; 7.940 ; 7.734 ; 8.398 ; 8.198 ; +; SW[5] ; VGA_G[1] ; 8.338 ; 8.135 ; 8.828 ; 8.625 ; +; SW[5] ; VGA_G[2] ; 8.027 ; 7.854 ; 8.486 ; 8.317 ; +; SW[5] ; VGA_G[3] ; 8.523 ; 8.328 ; 8.996 ; 8.819 ; +; SW[5] ; VGA_R[0] ; 7.974 ; 7.779 ; 8.516 ; 8.313 ; +; SW[5] ; VGA_R[1] ; 9.235 ; 9.102 ; 9.712 ; 9.593 ; +; SW[5] ; VGA_R[2] ; 7.813 ; 7.622 ; 8.323 ; 8.126 ; +; SW[5] ; VGA_R[3] ; 8.608 ; 8.420 ; 9.102 ; 8.909 ; ++------------+-------------+-------+-------+-------+-------+ + + ++----------------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; SW[4] ; VGA_B[0] ; 7.730 ; 7.546 ; 8.213 ; 8.023 ; +; SW[4] ; VGA_B[1] ; 7.362 ; 7.166 ; 7.831 ; 7.670 ; +; SW[4] ; VGA_B[2] ; 7.707 ; 7.513 ; 8.196 ; 8.002 ; +; SW[4] ; VGA_B[3] ; 7.241 ; 7.081 ; 7.716 ; 7.585 ; +; SW[4] ; VGA_G[0] ; 7.728 ; 7.530 ; 8.230 ; 8.026 ; +; SW[4] ; VGA_G[1] ; 7.726 ; 7.525 ; 8.195 ; 8.029 ; +; SW[4] ; VGA_G[2] ; 7.812 ; 7.643 ; 8.309 ; 8.134 ; +; SW[4] ; VGA_G[3] ; 7.449 ; 7.281 ; 7.953 ; 7.736 ; +; SW[4] ; VGA_R[0] ; 8.010 ; 7.817 ; 8.500 ; 8.307 ; +; SW[4] ; VGA_R[1] ; 7.887 ; 7.698 ; 8.361 ; 8.201 ; +; SW[4] ; VGA_R[2] ; 7.787 ; 7.597 ; 8.272 ; 8.079 ; +; SW[4] ; VGA_R[3] ; 7.704 ; 7.512 ; 8.180 ; 8.023 ; +; SW[5] ; VGA_B[0] ; 7.214 ; 7.022 ; 7.679 ; 7.522 ; +; SW[5] ; VGA_B[1] ; 8.030 ; 7.839 ; 8.479 ; 8.291 ; +; SW[5] ; VGA_B[2] ; 7.094 ; 6.898 ; 7.563 ; 7.395 ; +; SW[5] ; VGA_B[3] ; 8.233 ; 8.100 ; 8.707 ; 8.574 ; +; SW[5] ; VGA_G[0] ; 7.380 ; 7.180 ; 7.830 ; 7.658 ; +; SW[5] ; VGA_G[1] ; 8.066 ; 7.873 ; 8.527 ; 8.328 ; +; SW[5] ; VGA_G[2] ; 7.464 ; 7.293 ; 7.913 ; 7.770 ; +; SW[5] ; VGA_G[3] ; 8.210 ; 8.046 ; 8.679 ; 8.455 ; +; SW[5] ; VGA_R[0] ; 7.395 ; 7.200 ; 7.864 ; 7.697 ; +; SW[5] ; VGA_R[1] ; 8.881 ; 8.721 ; 9.373 ; 9.182 ; +; SW[5] ; VGA_R[2] ; 7.445 ; 7.250 ; 7.911 ; 7.751 ; +; SW[5] ; VGA_R[3] ; 8.375 ; 8.190 ; 8.830 ; 8.646 ; ++------------+-------------+-------+-------+-------+-------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Output Enable Times ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 3.114 ; 3.101 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 3.548 ; 3.535 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 3.114 ; 3.101 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 3.124 ; 3.111 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 3.271 ; 3.258 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 3.307 ; 3.294 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 3.114 ; 3.101 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 3.327 ; 3.314 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 3.291 ; 3.278 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 3.582 ; 3.569 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 3.582 ; 3.569 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 3.568 ; 3.555 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 3.572 ; 3.559 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 3.558 ; 3.545 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 3.568 ; 3.555 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 3.548 ; 3.535 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 3.307 ; 3.294 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Minimum Output Enable Times ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 2.246 ; 2.246 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.663 ; 2.663 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.246 ; 2.246 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.256 ; 2.256 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.398 ; 2.398 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.432 ; 2.432 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.246 ; 2.246 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.452 ; 2.452 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.417 ; 2.417 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.697 ; 2.697 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.697 ; 2.697 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.683 ; 2.683 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.687 ; 2.687 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.673 ; 2.673 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.683 ; 2.683 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.663 ; 2.663 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 2.432 ; 2.432 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Output Disable Times ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 3.128 ; 3.128 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 3.550 ; 3.550 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 3.128 ; 3.128 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 3.138 ; 3.138 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 3.266 ; 3.266 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 3.299 ; 3.299 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 3.128 ; 3.128 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 3.319 ; 3.319 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 3.289 ; 3.289 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 3.579 ; 3.579 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 3.579 ; 3.579 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 3.570 ; 3.570 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 3.569 ; 3.569 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 3.560 ; 3.560 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 3.570 ; 3.570 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 3.550 ; 3.550 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 3.299 ; 3.299 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Minimum Output Disable Times ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 2.260 ; 2.448 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.665 ; 2.853 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.260 ; 2.448 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.270 ; 2.458 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.393 ; 2.581 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.424 ; 2.612 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.260 ; 2.448 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.444 ; 2.632 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.415 ; 2.603 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.693 ; 2.881 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.693 ; 2.881 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.685 ; 2.873 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.683 ; 2.871 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.675 ; 2.863 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.685 ; 2.873 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.665 ; 2.853 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 2.424 ; 2.612 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ + + +---------------- +; MTBF Summary ; +---------------- +Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. +Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + +Number of Synchronizer Chains Found: 40 +Shortest Synchronizer Chain: 2 Registers +Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 +Worst Case Available Settling Time: 11.499 ns + +Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5 +Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9 + + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Synchronizer Summary ; ++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; Source Node ; Synchronization Node ; Worst-Case MTBF (Years) ; Typical MTBF (Years) ; Included in Design MTBF ; ++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; ++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ + + +Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.499 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; ; ; ; 6.941 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; ; ; ; 4.558 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.633 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; ; ; ; 7.339 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; ; ; ; 4.294 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.677 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; ; ; ; 7.337 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; ; ; ; 4.340 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.741 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; ; ; ; 6.945 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; ; ; ; 4.796 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.771 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; ; ; ; 7.199 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; ; ; ; 4.572 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.907 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; ; ; ; 7.334 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; ; ; ; 4.573 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.986 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; ; ; ; 7.338 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; ; ; ; 4.648 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 11.987 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; ; ; ; 7.336 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; ; ; ; 4.651 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.128 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; ; ; ; 7.336 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; ; ; ; 4.792 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.144 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; ; ; ; 7.339 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; ; ; ; 4.805 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.200 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; ; ; ; 7.197 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; ; ; ; 5.003 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.274 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; ; ; ; 7.336 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; ; ; ; 4.938 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.279 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; ; ; ; 7.198 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; ; ; ; 5.081 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.281 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; ; ; ; 6.783 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; ; ; ; 5.498 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.320 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; ; ; ; 7.197 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; ; ; ; 5.123 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.330 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; ; ; ; 7.269 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; ; ; ; 5.061 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.389 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; ; ; ; 7.017 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; ; ; ; 5.372 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.400 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; ; ; ; 7.337 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; ; ; ; 5.063 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.436 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; ; ; ; 7.199 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; ; ; ; 5.237 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.459 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; ; ; ; 7.199 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; ; ; ; 5.260 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.462 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; ; ; ; 7.352 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; ; ; ; 5.110 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.511 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; ; ; ; 7.095 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; ; ; ; 5.416 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.515 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; ; ; ; 7.018 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; ; ; ; 5.497 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.536 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; ; ; ; 7.211 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; ; ; ; 5.325 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.577 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; ; ; ; 7.198 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; ; ; ; 5.379 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.588 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; ; ; ; 7.218 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; ; ; ; 5.370 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.615 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; ; ; ; 7.017 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; ; ; ; 5.598 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.635 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; ; ; ; 7.214 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; ; ; ; 5.421 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.637 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; ; ; ; 7.098 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; ; ; ; 5.539 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.662 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; ; ; ; 7.253 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; ; ; ; 5.409 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.685 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; ; ; ; 7.200 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; ; ; ; 5.485 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.702 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; ; ; ; 7.112 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; ; ; ; 5.590 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.735 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; ; ; ; 7.222 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; ; ; ; 5.513 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.742 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; ; ; ; 7.077 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; ; ; ; 5.665 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.810 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; ; ; ; 7.197 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; ; ; ; 5.613 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.855 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; ; ; ; 7.198 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; ; ; ; 5.657 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.870 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; ; ; ; 7.336 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; ; ; ; 5.534 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.878 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; ; ; ; 7.238 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; ; ; ; 5.640 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 12.938 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; ; ; ; 7.018 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; ; ; ; 5.920 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.041 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; ; ; ; 7.077 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; ; ; ; 5.964 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + ++------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Setup Summary ; ++-----------------------------------------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+--------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 1.392 ; 0.000 ; +; CLOCK_50 ; 16.970 ; 0.000 ; ++-----------------------------------------------------+--------+---------------+ + + ++-----------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Hold Summary ; ++-----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+-------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.170 ; 0.000 ; +; CLOCK_50 ; 0.188 ; 0.000 ; ++-----------------------------------------------------+-------+---------------+ + + ++------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Recovery Summary ; ++-----------------------------------------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+--------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.783 ; 0.000 ; +; CLOCK_50 ; 16.478 ; 0.000 ; ++-----------------------------------------------------+--------+---------------+ + + ++-----------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Removal Summary ; ++-----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+-------+---------------+ +; CLOCK_50 ; 0.851 ; 0.000 ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 2.398 ; 0.000 ; ++-----------------------------------------------------+-------+---------------+ + + ++-----------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; ++-----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-----------------------------------------------------+-------+---------------+ +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.746 ; 0.000 ; +; CLOCK_50 ; 9.267 ; 0.000 ; ++-----------------------------------------------------+-------+---------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; 1.392 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.299 ; +; 1.392 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.299 ; +; 1.427 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.264 ; +; 1.427 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.316 ; 1.264 ; +; 1.432 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.074 ; +; 1.432 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.074 ; +; 1.432 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.074 ; +; 1.432 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.074 ; +; 1.432 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.074 ; +; 1.432 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.074 ; +; 1.432 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.074 ; +; 1.432 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.074 ; +; 1.432 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.074 ; +; 1.432 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.074 ; +; 1.432 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.074 ; +; 1.432 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.074 ; +; 1.432 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.074 ; +; 1.432 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.074 ; +; 1.432 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.501 ; 1.074 ; +; 1.468 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.322 ; 1.217 ; +; 1.477 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.224 ; +; 1.477 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.224 ; +; 1.477 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.224 ; +; 1.477 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.224 ; +; 1.477 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.224 ; +; 1.477 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.224 ; +; 1.477 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.224 ; +; 1.477 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.224 ; +; 1.477 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.224 ; +; 1.477 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.224 ; +; 1.477 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.224 ; +; 1.477 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.224 ; +; 1.477 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.224 ; +; 1.477 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.224 ; +; 1.477 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.306 ; 1.224 ; +; 1.498 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.305 ; 1.204 ; +; 1.498 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.305 ; 1.204 ; +; 1.498 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.305 ; 1.204 ; +; 1.498 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.305 ; 1.204 ; +; 1.498 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.305 ; 1.204 ; +; 1.498 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.305 ; 1.204 ; +; 1.498 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.305 ; 1.204 ; +; 1.498 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.305 ; 1.204 ; +; 1.498 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.305 ; 1.204 ; +; 1.498 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.305 ; 1.204 ; +; 1.498 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.305 ; 1.204 ; +; 1.498 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.305 ; 1.204 ; +; 1.498 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.305 ; 1.204 ; +; 1.498 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.305 ; 1.204 ; +; 1.498 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.305 ; 1.204 ; +; 1.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.317 ; 1.112 ; +; 1.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.317 ; 1.112 ; +; 1.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.317 ; 1.112 ; +; 1.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.317 ; 1.112 ; +; 1.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.317 ; 1.112 ; +; 1.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.317 ; 1.112 ; +; 1.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.317 ; 1.112 ; +; 1.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.317 ; 1.112 ; +; 1.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.317 ; 1.112 ; +; 1.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.317 ; 1.112 ; +; 1.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.317 ; 1.112 ; +; 1.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.317 ; 1.112 ; +; 1.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.317 ; 1.112 ; +; 1.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.317 ; 1.112 ; +; 1.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.317 ; 1.112 ; +; 1.618 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.305 ; 1.084 ; +; 1.618 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.305 ; 1.084 ; +; 1.618 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.305 ; 1.084 ; +; 1.618 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.305 ; 1.084 ; +; 1.618 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.305 ; 1.084 ; +; 1.618 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.305 ; 1.084 ; +; 1.618 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.305 ; 1.084 ; +; 1.632 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.312 ; 1.063 ; +; 1.632 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.312 ; 1.063 ; +; 1.632 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.312 ; 1.063 ; +; 1.668 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.298 ; 1.041 ; +; 1.668 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.298 ; 1.041 ; +; 1.668 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.298 ; 1.041 ; +; 1.669 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.321 ; 1.017 ; +; 1.669 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.321 ; 1.017 ; +; 1.669 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.321 ; 1.017 ; +; 4.603 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.159 ; 3.563 ; +; 4.605 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.158 ; 3.560 ; +; 4.665 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.159 ; 3.501 ; +; 4.669 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.138 ; 3.476 ; +; 4.669 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.138 ; 3.476 ; +; 4.685 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.159 ; 3.481 ; +; 4.685 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.158 ; 3.480 ; +; 4.686 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.159 ; 3.480 ; +; 4.687 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.158 ; 3.478 ; +; 4.691 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.057 ; 3.259 ; +; 4.691 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; -0.057 ; 3.259 ; +; 4.702 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.143 ; 3.448 ; +; 4.704 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.138 ; 3.441 ; +; 4.704 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.138 ; 3.441 ; +; 4.704 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.142 ; 3.445 ; +; 4.715 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.148 ; 3.440 ; +; 4.715 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.148 ; 3.440 ; +; 4.717 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.147 ; 3.437 ; +; 4.717 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000 ; 0.147 ; 3.437 ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Setup: 'CLOCK_50' ; ++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 16.970 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.991 ; +; 16.970 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.991 ; +; 16.970 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.991 ; +; 16.970 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.991 ; +; 16.970 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.991 ; +; 16.970 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.991 ; +; 16.970 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.991 ; +; 16.970 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.991 ; +; 16.970 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.991 ; +; 16.970 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.991 ; +; 16.970 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.991 ; +; 16.970 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.991 ; +; 16.970 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.991 ; +; 16.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.988 ; +; 16.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.988 ; +; 16.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.988 ; +; 16.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.988 ; +; 16.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.988 ; +; 16.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.988 ; +; 16.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.988 ; +; 16.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.988 ; +; 16.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.988 ; +; 16.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.988 ; +; 16.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.988 ; +; 16.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.988 ; +; 16.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.988 ; +; 17.035 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.926 ; +; 17.035 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.926 ; +; 17.035 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.926 ; +; 17.035 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.926 ; +; 17.035 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.926 ; +; 17.035 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.926 ; +; 17.035 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.926 ; +; 17.035 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.926 ; +; 17.035 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.926 ; +; 17.035 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.926 ; +; 17.035 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.926 ; +; 17.035 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.926 ; +; 17.035 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.926 ; +; 17.044 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.917 ; +; 17.047 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.914 ; +; 17.071 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.045 ; 2.891 ; +; 17.071 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.045 ; 2.891 ; +; 17.071 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.045 ; 2.891 ; +; 17.071 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.045 ; 2.891 ; +; 17.071 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.045 ; 2.891 ; +; 17.071 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.045 ; 2.891 ; +; 17.071 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.045 ; 2.891 ; +; 17.071 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.045 ; 2.891 ; +; 17.071 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.045 ; 2.891 ; +; 17.071 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.045 ; 2.891 ; +; 17.071 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.045 ; 2.891 ; +; 17.071 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.045 ; 2.891 ; +; 17.071 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.045 ; 2.891 ; +; 17.100 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.871 ; +; 17.100 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.871 ; +; 17.100 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.871 ; +; 17.100 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.871 ; +; 17.100 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.871 ; +; 17.100 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.871 ; +; 17.100 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.871 ; +; 17.100 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.871 ; +; 17.100 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.871 ; +; 17.100 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.871 ; +; 17.100 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.871 ; +; 17.100 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.871 ; +; 17.100 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.871 ; +; 17.100 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.871 ; +; 17.100 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.871 ; +; 17.100 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.871 ; +; 17.108 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.853 ; +; 17.108 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.853 ; +; 17.108 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.853 ; +; 17.108 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.853 ; +; 17.108 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.853 ; +; 17.108 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.853 ; +; 17.108 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.853 ; +; 17.108 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.853 ; +; 17.108 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.853 ; +; 17.108 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.853 ; +; 17.108 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.853 ; +; 17.108 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.853 ; +; 17.108 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.853 ; +; 17.109 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.046 ; 2.852 ; +; 17.110 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.861 ; +; 17.110 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.861 ; +; 17.110 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.861 ; +; 17.110 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.861 ; +; 17.110 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.861 ; +; 17.110 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.861 ; +; 17.110 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.861 ; +; 17.110 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.861 ; +; 17.110 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.861 ; +; 17.110 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.861 ; +; 17.110 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.861 ; +; 17.110 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.861 ; +; 17.110 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.861 ; +; 17.110 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.861 ; +; 17.110 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.861 ; +; 17.110 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.036 ; 2.861 ; ++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ +; 0.170 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.230 ; 0.484 ; +; 0.178 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.220 ; 0.502 ; +; 0.179 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.220 ; 0.503 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.307 ; +; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 0.307 ; +; 0.183 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.216 ; 0.503 ; +; 0.185 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 0.313 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 0.315 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.314 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 0.315 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.314 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.314 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.314 ; +; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.314 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.315 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.315 ; +; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.307 ; +; 0.190 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.317 ; +; 0.190 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.230 ; 0.504 ; +; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.313 ; +; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[15] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.314 ; +; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.314 ; +; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[17] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.314 ; +; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|BA[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.314 ; +; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_done ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.314 ; +; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.314 ; +; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.314 ; +; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.314 ; +; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.314 ; +; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.314 ; +; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.314 ; +; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[6] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.314 ; +; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.036 ; 0.315 ; +; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[10] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.314 ; +; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.518 ; +; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.314 ; +; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.314 ; +; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.314 ; +; 0.196 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.315 ; +; 0.196 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 0.324 ; +; 0.196 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REFRESH ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_refresh ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.315 ; +; 0.196 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_shift[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.315 ; +; 0.197 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[16] ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[8] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.316 ; +; 0.197 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|RAS_N ; DE0_D5M:inst|Sdram_Control_4Port:u7|RAS_N ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.316 ; +; 0.197 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.324 ; +; 0.198 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.325 ; +; 0.198 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 0.325 ; +; 0.198 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 0.317 ; ++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Hold: 'CLOCK_50' ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 0.188 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.307 ; +; 0.188 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.307 ; +; 0.194 ; DE0_D5M:inst|Reset_Delay:u2|Cont[0] ; DE0_D5M:inst|Reset_Delay:u2|Cont[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.314 ; +; 0.195 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.314 ; +; 0.195 ; ps2:inst6|clk_div[0] ; ps2:inst6|clk_div[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.314 ; +; 0.196 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.315 ; +; 0.201 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.022 ; 0.307 ; +; 0.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.324 ; +; 0.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.325 ; +; 0.208 ; DE0_D5M:inst|rClk[0] ; DE0_D5M:inst|rClk[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.022 ; 0.314 ; +; 0.231 ; ps2:inst6|clk_div[8] ; ps2:inst6|clk_div[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.022 ; 0.337 ; +; 0.272 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.391 ; +; 0.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.413 ; +; 0.295 ; ps2:inst6|clk_div[4] ; ps2:inst6|clk_div[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.414 ; +; 0.296 ; ps2:inst6|clk_div[6] ; ps2:inst6|clk_div[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.415 ; +; 0.296 ; ps2:inst6|clk_div[3] ; ps2:inst6|clk_div[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.415 ; +; 0.296 ; ps2:inst6|clk_div[2] ; ps2:inst6|clk_div[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.415 ; +; 0.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.417 ; +; 0.297 ; ps2:inst6|clk_div[7] ; ps2:inst6|clk_div[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.416 ; +; 0.297 ; ps2:inst6|clk_div[5] ; ps2:inst6|clk_div[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.416 ; +; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.418 ; +; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.418 ; +; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.418 ; +; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.417 ; +; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.417 ; +; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.417 ; +; 0.298 ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.418 ; +; 0.298 ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.418 ; +; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.419 ; +; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.419 ; +; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.419 ; +; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.419 ; +; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.418 ; +; 0.299 ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.419 ; +; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.420 ; +; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.420 ; +; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.419 ; +; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.419 ; +; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.419 ; +; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.419 ; +; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.419 ; +; 0.300 ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.420 ; +; 0.301 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.421 ; +; 0.301 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.420 ; +; 0.301 ; ps2:inst6|clk_div[1] ; ps2:inst6|clk_div[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.420 ; +; 0.302 ; ps2:inst6|clk_div[0] ; ps2:inst6|clk_div[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.421 ; +; 0.304 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.424 ; +; 0.304 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.424 ; +; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; DE0_D5M:inst|Reset_Delay:u2|Cont[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[14] ; DE0_D5M:inst|Reset_Delay:u2|Cont[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.425 ; +; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.425 ; +; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.426 ; +; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.426 ; +; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.427 ; +; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.427 ; +; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.427 ; +; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.427 ; +; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.427 ; +; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.426 ; +; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[9] ; DE0_D5M:inst|Reset_Delay:u2|Cont[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.427 ; +; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.427 ; +; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.427 ; +; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.427 ; +; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.036 ; 0.428 ; +; 0.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.431 ; +; 0.316 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.435 ; +; 0.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.436 ; +; 0.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.436 ; +; 0.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.437 ; +; 0.319 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.438 ; +; 0.319 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.438 ; +; 0.369 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.035 ; 0.488 ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; 0.783 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.364 ; 1.828 ; +; 0.783 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.364 ; 1.828 ; +; 0.783 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.364 ; 1.828 ; +; 0.783 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.364 ; 1.828 ; +; 0.783 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.364 ; 1.828 ; +; 0.783 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.364 ; 1.828 ; +; 0.783 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.364 ; 1.828 ; +; 0.783 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.364 ; 1.828 ; +; 0.783 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.364 ; 1.828 ; +; 0.783 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.364 ; 1.828 ; +; 0.783 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.364 ; 1.828 ; +; 0.783 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.364 ; 1.828 ; +; 0.783 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.364 ; 1.828 ; +; 0.783 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.364 ; 1.828 ; +; 0.783 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.364 ; 1.828 ; +; 0.783 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.364 ; 1.828 ; +; 0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.825 ; +; 0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.825 ; +; 0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.825 ; +; 0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.825 ; +; 0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.825 ; +; 0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.825 ; +; 0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.825 ; +; 0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.825 ; +; 0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.825 ; +; 0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.825 ; +; 0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.825 ; +; 0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.825 ; +; 0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.825 ; +; 0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.825 ; +; 0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.825 ; +; 0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.825 ; +; 0.819 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.364 ; 1.846 ; +; 0.826 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.360 ; 1.843 ; +; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.499 ; 1.652 ; +; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.499 ; 1.652 ; +; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.499 ; 1.652 ; +; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.499 ; 1.652 ; +; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.499 ; 1.652 ; +; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.499 ; 1.652 ; +; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.499 ; 1.652 ; +; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.499 ; 1.652 ; +; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.499 ; 1.652 ; +; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.499 ; 1.652 ; +; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.499 ; 1.652 ; +; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.499 ; 1.652 ; +; 0.863 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.506 ; 1.638 ; +; 0.863 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.506 ; 1.638 ; +; 0.863 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.506 ; 1.638 ; +; 0.863 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.506 ; 1.638 ; +; 0.863 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.506 ; 1.638 ; +; 0.863 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.506 ; 1.638 ; +; 0.863 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.506 ; 1.638 ; +; 0.863 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.506 ; 1.638 ; +; 0.863 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.506 ; 1.638 ; +; 0.863 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.506 ; 1.638 ; +; 0.863 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.506 ; 1.638 ; +; 0.863 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.506 ; 1.638 ; +; 0.864 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.506 ; 1.637 ; +; 0.864 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.506 ; 1.637 ; +; 0.864 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.506 ; 1.637 ; +; 0.864 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.506 ; 1.637 ; +; 0.864 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.506 ; 1.637 ; +; 0.864 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.503 ; 1.640 ; +; 0.864 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.503 ; 1.640 ; +; 0.864 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.503 ; 1.640 ; +; 0.864 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.503 ; 1.640 ; +; 0.864 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.503 ; 1.640 ; +; 0.864 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.503 ; 1.640 ; +; 0.864 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.503 ; 1.640 ; +; 0.865 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.503 ; 1.639 ; +; 0.865 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.503 ; 1.639 ; +; 0.865 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.503 ; 1.639 ; +; 0.865 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.503 ; 1.639 ; +; 0.865 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.503 ; 1.639 ; +; 0.865 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.503 ; 1.639 ; +; 0.865 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.503 ; 1.639 ; +; 0.865 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.503 ; 1.639 ; +; 0.865 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.503 ; 1.639 ; +; 0.865 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.503 ; 1.639 ; +; 0.865 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.503 ; 1.639 ; +; 0.865 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.503 ; 1.639 ; +; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.497 ; 1.643 ; +; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.497 ; 1.643 ; +; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.496 ; 1.644 ; +; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.496 ; 1.644 ; +; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.496 ; 1.644 ; +; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.497 ; 1.643 ; +; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.497 ; 1.643 ; +; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.497 ; 1.643 ; +; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.497 ; 1.643 ; +; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.497 ; 1.643 ; +; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.496 ; 1.644 ; +; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.497 ; 1.643 ; +; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.497 ; 1.643 ; +; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.497 ; 1.643 ; +; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.497 ; 1.643 ; +; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.497 ; 1.643 ; +; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.497 ; 1.643 ; +; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000 ; -1.497 ; 1.643 ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Recovery: 'CLOCK_50' ; ++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 16.478 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.498 ; 3.031 ; +; 16.481 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.498 ; 3.028 ; +; 16.543 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.498 ; 2.966 ; +; 16.579 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.497 ; 2.931 ; +; 16.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.498 ; 2.893 ; +; 16.660 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.497 ; 2.850 ; +; 16.662 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.497 ; 2.848 ; +; 16.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.497 ; 2.847 ; +; 16.723 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.497 ; 2.787 ; +; 16.725 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.497 ; 2.785 ; +; 16.797 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.497 ; 2.713 ; +; 16.798 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.497 ; 2.712 ; +; 16.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.497 ; 2.711 ; +; 16.800 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.497 ; 2.710 ; +; 16.863 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.497 ; 2.647 ; +; 16.934 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.497 ; 2.576 ; +; 16.994 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.498 ; 2.515 ; +; 17.068 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.498 ; 2.441 ; +; 17.075 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.498 ; 2.434 ; +; 17.079 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.498 ; 2.430 ; +; 17.114 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.855 ; +; 17.114 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.855 ; +; 17.114 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.855 ; +; 17.114 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.855 ; +; 17.114 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.855 ; +; 17.114 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.855 ; +; 17.114 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.855 ; +; 17.114 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.855 ; +; 17.114 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.855 ; +; 17.114 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.855 ; +; 17.114 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.855 ; +; 17.114 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.855 ; +; 17.114 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.855 ; +; 17.114 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.855 ; +; 17.114 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.855 ; +; 17.114 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.855 ; +; 17.117 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.852 ; +; 17.117 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.852 ; +; 17.117 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.852 ; +; 17.117 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.852 ; +; 17.117 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.852 ; +; 17.117 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.852 ; +; 17.117 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.852 ; +; 17.117 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.852 ; +; 17.117 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.852 ; +; 17.117 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.852 ; +; 17.117 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.852 ; +; 17.117 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.852 ; +; 17.117 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.852 ; +; 17.117 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.852 ; +; 17.117 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.852 ; +; 17.117 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.852 ; +; 17.123 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.498 ; 2.386 ; +; 17.140 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.498 ; 2.369 ; +; 17.146 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.498 ; 2.363 ; +; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.790 ; +; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.790 ; +; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.790 ; +; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.790 ; +; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.790 ; +; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.790 ; +; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.790 ; +; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.790 ; +; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.790 ; +; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.790 ; +; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.790 ; +; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.790 ; +; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.790 ; +; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.790 ; +; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.790 ; +; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.790 ; +; 17.213 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.498 ; 2.296 ; +; 17.215 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.037 ; 2.755 ; +; 17.215 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.037 ; 2.755 ; +; 17.215 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.037 ; 2.755 ; +; 17.215 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.037 ; 2.755 ; +; 17.215 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.037 ; 2.755 ; +; 17.215 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.037 ; 2.755 ; +; 17.215 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.037 ; 2.755 ; +; 17.215 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.037 ; 2.755 ; +; 17.215 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.037 ; 2.755 ; +; 17.215 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.037 ; 2.755 ; +; 17.215 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.037 ; 2.755 ; +; 17.215 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.037 ; 2.755 ; +; 17.215 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.037 ; 2.755 ; +; 17.215 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.037 ; 2.755 ; +; 17.215 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.037 ; 2.755 ; +; 17.215 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.037 ; 2.755 ; +; 17.252 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.717 ; +; 17.252 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.717 ; +; 17.252 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.717 ; +; 17.252 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.717 ; +; 17.252 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.717 ; +; 17.252 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.717 ; +; 17.252 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.717 ; +; 17.252 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.717 ; +; 17.252 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.717 ; +; 17.252 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.717 ; +; 17.252 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.717 ; +; 17.252 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.038 ; 2.717 ; ++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Removal: 'CLOCK_50' ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 0.851 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 0.969 ; +; 0.851 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 0.969 ; +; 0.851 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 0.969 ; +; 0.851 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 0.969 ; +; 0.851 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 0.969 ; +; 0.851 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 0.969 ; +; 0.851 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 0.969 ; +; 0.851 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 0.969 ; +; 0.851 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 0.969 ; +; 0.851 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 0.969 ; +; 0.851 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 0.969 ; +; 0.851 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 0.969 ; +; 0.851 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 0.969 ; +; 0.851 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 0.969 ; +; 0.851 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 0.969 ; +; 0.851 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 0.969 ; +; 0.996 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 1.114 ; +; 0.996 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 1.114 ; +; 0.996 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 1.114 ; +; 0.996 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 1.114 ; +; 0.996 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 1.114 ; +; 0.996 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 1.114 ; +; 0.996 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 1.114 ; +; 0.996 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 1.114 ; +; 0.996 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 1.114 ; +; 0.996 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 1.114 ; +; 0.996 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 1.114 ; +; 0.996 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 1.114 ; +; 0.996 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 1.114 ; +; 0.996 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 1.114 ; +; 0.996 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 1.114 ; +; 0.996 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 1.114 ; +; 1.225 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.043 ; 1.352 ; +; 1.225 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.043 ; 1.352 ; +; 1.225 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.043 ; 1.352 ; +; 1.225 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.043 ; 1.352 ; +; 1.231 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.043 ; 1.358 ; +; 1.231 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.043 ; 1.358 ; +; 1.231 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.043 ; 1.358 ; +; 1.231 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.043 ; 1.358 ; +; 1.231 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.043 ; 1.358 ; +; 1.231 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.043 ; 1.358 ; +; 1.231 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.043 ; 1.358 ; +; 1.231 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.043 ; 1.358 ; +; 1.231 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.043 ; 1.358 ; +; 1.231 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.043 ; 1.358 ; +; 1.231 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.043 ; 1.358 ; +; 1.231 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.043 ; 1.358 ; +; 1.267 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.044 ; 1.395 ; +; 1.267 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.044 ; 1.395 ; +; 1.267 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.044 ; 1.395 ; +; 1.267 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.044 ; 1.395 ; +; 1.267 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.044 ; 1.395 ; +; 1.267 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.044 ; 1.395 ; +; 1.267 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.044 ; 1.395 ; +; 1.267 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.044 ; 1.395 ; +; 1.267 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.044 ; 1.395 ; +; 1.267 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.044 ; 1.395 ; +; 1.267 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.044 ; 1.395 ; +; 1.267 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.044 ; 1.395 ; +; 1.267 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.044 ; 1.395 ; +; 1.413 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.033 ; 1.530 ; +; 1.413 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.033 ; 1.530 ; +; 1.413 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.033 ; 1.530 ; +; 1.413 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.033 ; 1.530 ; +; 1.413 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.033 ; 1.530 ; +; 1.413 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.033 ; 1.530 ; +; 1.413 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.033 ; 1.530 ; +; 1.413 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.033 ; 1.530 ; +; 1.413 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.033 ; 1.530 ; +; 1.413 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.033 ; 1.530 ; +; 1.413 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.033 ; 1.530 ; +; 1.413 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.033 ; 1.530 ; +; 1.413 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.033 ; 1.530 ; +; 1.413 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.033 ; 1.530 ; +; 1.454 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 0.000 ; -0.417 ; 1.121 ; +; 1.604 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK ; CLOCK_50 ; CLOCK_50 ; 0.000 ; -0.417 ; 1.271 ; +; 1.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.810 ; +; 1.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.810 ; +; 1.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.810 ; +; 1.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.810 ; +; 1.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.810 ; +; 1.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.810 ; +; 1.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.810 ; +; 1.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.810 ; +; 1.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.810 ; +; 1.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.810 ; +; 1.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.810 ; +; 1.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.810 ; +; 1.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.810 ; +; 1.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.810 ; +; 1.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.810 ; +; 1.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 1.810 ; +; 1.704 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 1.822 ; +; 1.704 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 1.822 ; +; 1.704 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 1.822 ; +; 1.704 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 1.822 ; +; 1.704 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 1.822 ; +; 1.704 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 1.822 ; +; 1.704 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.034 ; 1.822 ; ++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ +; 2.398 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.007 ; 1.475 ; +; 2.398 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.007 ; 1.475 ; +; 2.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.004 ; 1.485 ; +; 2.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.004 ; 1.485 ; +; 2.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.004 ; 1.485 ; +; 2.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.004 ; 1.485 ; +; 2.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.004 ; 1.485 ; +; 2.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.004 ; 1.485 ; +; 2.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.004 ; 1.485 ; +; 2.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.004 ; 1.485 ; +; 2.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.004 ; 1.485 ; +; 2.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.004 ; 1.485 ; +; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.477 ; +; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.477 ; +; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.477 ; +; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.477 ; +; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.477 ; +; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.477 ; +; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.017 ; 1.476 ; +; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.017 ; 1.476 ; +; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.017 ; 1.476 ; +; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.017 ; 1.476 ; +; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.017 ; 1.476 ; +; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.477 ; +; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.477 ; +; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.017 ; 1.476 ; +; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.017 ; 1.476 ; +; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.477 ; +; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.477 ; +; 2.410 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.009 ; 1.485 ; +; 2.410 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.009 ; 1.485 ; +; 2.410 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.009 ; 1.485 ; +; 2.410 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.009 ; 1.485 ; +; 2.410 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.009 ; 1.485 ; +; 2.410 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.009 ; 1.485 ; +; 2.410 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.009 ; 1.485 ; +; 2.410 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.009 ; 1.485 ; +; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.012 ; 1.483 ; +; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.012 ; 1.483 ; +; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.012 ; 1.483 ; +; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.012 ; 1.483 ; +; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.012 ; 1.483 ; +; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.017 ; 1.478 ; +; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.017 ; 1.478 ; +; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.017 ; 1.478 ; +; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.017 ; 1.478 ; +; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.017 ; 1.478 ; +; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.017 ; 1.478 ; +; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.017 ; 1.478 ; +; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.017 ; 1.478 ; +; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.017 ; 1.478 ; +; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.017 ; 1.478 ; +; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.017 ; 1.478 ; +; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.017 ; 1.478 ; +; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.017 ; 1.478 ; +; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.012 ; 1.483 ; +; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.019 ; 1.480 ; +; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.019 ; 1.480 ; +; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.019 ; 1.480 ; +; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.019 ; 1.480 ; +; 2.417 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.010 ; 1.491 ; +; 2.417 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.010 ; 1.491 ; +; 2.417 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.010 ; 1.491 ; +; 2.417 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.010 ; 1.491 ; +; 2.417 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.010 ; 1.491 ; +; 2.417 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.010 ; 1.491 ; +; 2.417 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.010 ; 1.491 ; +; 2.417 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.010 ; 1.491 ; +; 2.417 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.010 ; 1.491 ; +; 2.419 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9 ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.018 ; 1.485 ; +; 2.419 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.018 ; 1.485 ; +; 2.419 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.018 ; 1.485 ; +; 2.419 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.018 ; 1.485 ; +; 2.419 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.018 ; 1.485 ; +; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.490 ; +; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.490 ; +; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.490 ; +; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.490 ; +; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.490 ; +; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.490 ; +; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.490 ; +; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.490 ; +; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.490 ; +; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.490 ; +; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.490 ; +; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.491 ; +; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.491 ; +; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.491 ; +; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.491 ; +; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.491 ; +; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.491 ; +; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.491 ; +; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.491 ; +; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.491 ; +; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.491 ; +; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.491 ; +; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.491 ; +; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.491 ; +; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.491 ; +; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5] ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; -1.016 ; 1.491 ; ++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+--------------+----------------+-----------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++-------+--------------+----------------+-----------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; 3.746 ; 3.976 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; +; 3.746 ; 3.976 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_we_reg ; +; 3.746 ; 3.976 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0 ; +; 3.746 ; 3.976 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_we_reg ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0 ; +; 3.748 ; 3.978 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0 ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9] ; +; 3.749 ; 3.979 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ; +; 3.752 ; 3.982 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0] ; +; 3.752 ; 3.982 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10] ; +; 3.752 ; 3.982 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11] ; +; 3.752 ; 3.982 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12] ; +; 3.752 ; 3.982 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13] ; +; 3.752 ; 3.982 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14] ; +; 3.752 ; 3.982 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15] ; +; 3.752 ; 3.982 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1] ; +; 3.752 ; 3.982 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2] ; +; 3.752 ; 3.982 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3] ; +; 3.752 ; 3.982 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4] ; +; 3.752 ; 3.982 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5] ; +; 3.752 ; 3.982 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6] ; +; 3.752 ; 3.982 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7] ; +; 3.752 ; 3.982 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8] ; +; 3.752 ; 3.982 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9] ; +; 3.752 ; 3.982 ; 0.230 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ; +; 3.779 ; 3.963 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0] ; +; 3.779 ; 3.963 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1] ; +; 3.779 ; 3.963 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0] ; +; 3.779 ; 3.963 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1] ; +; 3.779 ; 3.963 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2] ; +; 3.779 ; 3.963 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3] ; +; 3.779 ; 3.963 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4] ; +; 3.779 ; 3.963 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5] ; +; 3.779 ; 3.963 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6] ; +; 3.779 ; 3.963 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[8] ; +; 3.779 ; 3.963 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0] ; +; 3.779 ; 3.963 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1] ; +; 3.779 ; 3.963 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[9] ; +; 3.779 ; 3.963 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8] ; +; 3.780 ; 3.964 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[8] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; +; 3.781 ; 3.965 ; 0.184 ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; ++-------+--------------+----------------+-----------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' ; ++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+ +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[0] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[16] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[17] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[18] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[19] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[20] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[21] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[22] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[23] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[24] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[25] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[26] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[27] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[28] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[29] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[30] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[31] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|oRST_1 ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|oRST_2 ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[0] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[1] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[2] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[3] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[4] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[5] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[6] ; +; 9.267 ; 9.451 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; ps2:inst6|clk_div[7] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[10] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[11] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[12] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[13] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[14] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[15] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[1] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[2] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[3] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[4] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[5] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[6] ; +; 9.268 ; 9.452 ; 0.184 ; Low Pulse Width ; CLOCK_50 ; Rise ; DE0_D5M:inst|Reset_Delay:u2|Cont[7] ; ++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Setup Times ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; SW[*] ; CLOCK_50 ; 2.291 ; 3.215 ; Rise ; CLOCK_50 ; +; SW[0] ; CLOCK_50 ; 2.291 ; 3.215 ; Rise ; CLOCK_50 ; +; SW[1] ; CLOCK_50 ; 2.282 ; 3.091 ; Rise ; CLOCK_50 ; +; DRAM_DQ[*] ; CLOCK_50 ; 2.415 ; 3.254 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.288 ; 3.103 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.152 ; 2.950 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.201 ; 2.947 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.248 ; 3.046 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.415 ; 3.254 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.122 ; 2.871 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.297 ; 3.095 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.118 ; 2.868 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.143 ; 2.892 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.141 ; 2.938 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.144 ; 2.895 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.141 ; 2.894 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.229 ; 2.973 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.138 ; 2.888 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.249 ; 3.019 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------+ +; Hold Times ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ +; SW[*] ; CLOCK_50 ; -1.138 ; -1.987 ; Rise ; CLOCK_50 ; +; SW[0] ; CLOCK_50 ; -1.174 ; -2.007 ; Rise ; CLOCK_50 ; +; SW[1] ; CLOCK_50 ; -1.138 ; -1.987 ; Rise ; CLOCK_50 ; +; DRAM_DQ[*] ; CLOCK_50 ; -1.725 ; -2.460 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; -1.890 ; -2.688 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; -1.745 ; -2.526 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; -1.811 ; -2.549 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; -1.842 ; -2.630 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; -1.997 ; -2.818 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; -1.730 ; -2.464 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; -1.899 ; -2.681 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; -1.725 ; -2.460 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; -1.751 ; -2.485 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; -1.733 ; -2.513 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; -1.752 ; -2.489 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; -1.748 ; -2.486 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; -1.839 ; -2.575 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; -1.746 ; -2.481 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; -1.852 ; -2.606 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------+ +; Clock to Output Times ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; GPIO_1[*] ; CLOCK_50 ; 3.775 ; 3.846 ; Rise ; CLOCK_50 ; +; GPIO_1[14] ; CLOCK_50 ; 3.773 ; 3.846 ; Rise ; CLOCK_50 ; +; GPIO_1[20] ; CLOCK_50 ; 3.775 ; 3.734 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[*] ; CLOCK_50 ; 3.358 ; 3.454 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[0] ; CLOCK_50 ; 3.358 ; 3.454 ; Rise ; CLOCK_50 ; +; VGA_CLK ; CLOCK_50 ; 3.341 ; 3.261 ; Rise ; CLOCK_50 ; +; DRAM_ADDR[*] ; CLOCK_50 ; 2.064 ; 2.040 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[0] ; CLOCK_50 ; 2.048 ; 2.025 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[1] ; CLOCK_50 ; 2.064 ; 2.040 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[2] ; CLOCK_50 ; 2.051 ; 2.023 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[3] ; CLOCK_50 ; 2.045 ; 2.017 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[4] ; CLOCK_50 ; 1.947 ; 1.917 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[5] ; CLOCK_50 ; 1.928 ; 1.892 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[6] ; CLOCK_50 ; 1.835 ; 1.793 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[7] ; CLOCK_50 ; 1.846 ; 1.805 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[8] ; CLOCK_50 ; 1.824 ; 1.783 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[9] ; CLOCK_50 ; 1.835 ; 1.794 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[10] ; CLOCK_50 ; 1.980 ; 1.954 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[11] ; CLOCK_50 ; 1.826 ; 1.785 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_0 ; CLOCK_50 ; 1.887 ; 1.861 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_1 ; CLOCK_50 ; 1.977 ; 1.961 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CAS_N ; CLOCK_50 ; 1.924 ; 1.896 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CS_N ; CLOCK_50 ; 2.148 ; 2.162 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[*] ; CLOCK_50 ; 4.843 ; 4.633 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 3.565 ; 3.488 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 3.560 ; 3.597 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 3.378 ; 3.355 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 4.843 ; 4.633 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 3.442 ; 3.441 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 3.561 ; 3.567 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 3.557 ; 3.480 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 3.484 ; 3.501 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 3.496 ; 3.477 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 3.538 ; 3.529 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 3.603 ; 3.588 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 3.646 ; 3.586 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 3.640 ; 3.640 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 3.635 ; 3.633 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 3.562 ; 3.486 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 3.545 ; 3.522 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_LDQM ; CLOCK_50 ; 2.063 ; 2.042 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_RAS_N ; CLOCK_50 ; 2.028 ; 2.008 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_UDQM ; CLOCK_50 ; 2.031 ; 2.013 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 3.470 ; 3.239 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CLK ; CLOCK_50 ; -1.313 ; ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; +; DRAM_CLK ; CLOCK_50 ; ; -1.366 ; Fall ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; GPIO_1[*] ; CLOCK_50 ; 3.685 ; 3.643 ; Rise ; CLOCK_50 ; +; GPIO_1[14] ; CLOCK_50 ; 3.685 ; 3.753 ; Rise ; CLOCK_50 ; +; GPIO_1[20] ; CLOCK_50 ; 3.686 ; 3.643 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[*] ; CLOCK_50 ; 3.286 ; 3.374 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[0] ; CLOCK_50 ; 3.286 ; 3.374 ; Rise ; CLOCK_50 ; +; VGA_CLK ; CLOCK_50 ; 3.266 ; 3.193 ; Rise ; CLOCK_50 ; +; DRAM_ADDR[*] ; CLOCK_50 ; 1.574 ; 1.532 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[0] ; CLOCK_50 ; 1.789 ; 1.764 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[1] ; CLOCK_50 ; 1.806 ; 1.779 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[2] ; CLOCK_50 ; 1.794 ; 1.763 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[3] ; CLOCK_50 ; 1.787 ; 1.756 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[4] ; CLOCK_50 ; 1.694 ; 1.661 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[5] ; CLOCK_50 ; 1.674 ; 1.636 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[6] ; CLOCK_50 ; 1.585 ; 1.542 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[7] ; CLOCK_50 ; 1.595 ; 1.553 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[8] ; CLOCK_50 ; 1.574 ; 1.532 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[9] ; CLOCK_50 ; 1.584 ; 1.542 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[10] ; CLOCK_50 ; 1.725 ; 1.696 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[11] ; CLOCK_50 ; 1.575 ; 1.533 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_0 ; CLOCK_50 ; 1.634 ; 1.607 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_1 ; CLOCK_50 ; 1.720 ; 1.702 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CAS_N ; CLOCK_50 ; 1.670 ; 1.640 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CS_N ; CLOCK_50 ; 1.883 ; 1.893 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[*] ; CLOCK_50 ; 2.138 ; 2.126 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.138 ; 2.126 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.630 ; 2.712 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.422 ; 2.456 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 3.881 ; 3.708 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.479 ; 2.515 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.549 ; 2.620 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.472 ; 2.507 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.545 ; 2.606 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.366 ; 2.385 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.394 ; 2.422 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.457 ; 2.478 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.394 ; 2.427 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.622 ; 2.676 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.497 ; 2.535 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.304 ; 2.306 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 2.395 ; 2.416 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_LDQM ; CLOCK_50 ; 1.803 ; 1.779 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_RAS_N ; CLOCK_50 ; 1.770 ; 1.747 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_UDQM ; CLOCK_50 ; 1.772 ; 1.752 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 3.215 ; 2.983 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CLK ; CLOCK_50 ; -1.537 ; ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; +; DRAM_CLK ; CLOCK_50 ; ; -1.591 ; Fall ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; SW[4] ; VGA_B[0] ; 5.032 ; 5.020 ; 5.918 ; 5.899 ; +; SW[4] ; VGA_B[1] ; 4.956 ; 4.945 ; 5.792 ; 5.781 ; +; SW[4] ; VGA_B[2] ; 5.017 ; 5.003 ; 5.903 ; 5.882 ; +; SW[4] ; VGA_B[3] ; 5.082 ; 5.107 ; 5.940 ; 5.981 ; +; SW[4] ; VGA_G[0] ; 5.061 ; 5.043 ; 5.894 ; 5.883 ; +; SW[4] ; VGA_G[1] ; 5.253 ; 5.269 ; 6.121 ; 6.137 ; +; SW[4] ; VGA_G[2] ; 5.125 ; 5.123 ; 5.958 ; 5.963 ; +; SW[4] ; VGA_G[3] ; 5.388 ; 5.380 ; 6.256 ; 6.248 ; +; SW[4] ; VGA_R[0] ; 5.219 ; 5.219 ; 6.105 ; 6.098 ; +; SW[4] ; VGA_R[1] ; 5.347 ; 5.431 ; 6.167 ; 6.244 ; +; SW[4] ; VGA_R[2] ; 5.068 ; 5.067 ; 5.906 ; 5.905 ; +; SW[4] ; VGA_R[3] ; 5.195 ; 5.209 ; 6.029 ; 6.043 ; +; SW[5] ; VGA_B[0] ; 4.781 ; 4.762 ; 5.604 ; 5.585 ; +; SW[5] ; VGA_B[1] ; 5.196 ; 5.185 ; 6.071 ; 6.060 ; +; SW[5] ; VGA_B[2] ; 4.825 ; 4.811 ; 5.685 ; 5.664 ; +; SW[5] ; VGA_B[3] ; 5.391 ; 5.416 ; 6.284 ; 6.325 ; +; SW[5] ; VGA_G[0] ; 4.979 ; 4.961 ; 5.825 ; 5.807 ; +; SW[5] ; VGA_G[1] ; 5.231 ; 5.247 ; 6.094 ; 6.110 ; +; SW[5] ; VGA_G[2] ; 5.040 ; 5.038 ; 5.886 ; 5.884 ; +; SW[5] ; VGA_G[3] ; 5.365 ; 5.357 ; 6.229 ; 6.221 ; +; SW[5] ; VGA_R[0] ; 5.023 ; 5.023 ; 5.882 ; 5.875 ; +; SW[5] ; VGA_R[1] ; 5.813 ; 5.897 ; 6.699 ; 6.785 ; +; SW[5] ; VGA_R[2] ; 4.937 ; 4.936 ; 5.760 ; 5.759 ; +; SW[5] ; VGA_R[3] ; 5.436 ; 5.450 ; 6.313 ; 6.327 ; ++------------+-------------+-------+-------+-------+-------+ + + ++----------------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; SW[4] ; VGA_B[0] ; 4.871 ; 4.857 ; 5.715 ; 5.701 ; +; SW[4] ; VGA_B[1] ; 4.662 ; 4.640 ; 5.472 ; 5.476 ; +; SW[4] ; VGA_B[2] ; 4.854 ; 4.839 ; 5.699 ; 5.684 ; +; SW[4] ; VGA_B[3] ; 4.588 ; 4.587 ; 5.391 ; 5.410 ; +; SW[4] ; VGA_G[0] ; 4.860 ; 4.847 ; 5.716 ; 5.696 ; +; SW[4] ; VGA_G[1] ; 4.861 ; 4.865 ; 5.688 ; 5.718 ; +; SW[4] ; VGA_G[2] ; 4.920 ; 4.923 ; 5.775 ; 5.771 ; +; SW[4] ; VGA_G[3] ; 4.699 ; 4.697 ; 5.557 ; 5.518 ; +; SW[4] ; VGA_R[0] ; 5.048 ; 5.046 ; 5.894 ; 5.892 ; +; SW[4] ; VGA_R[1] ; 4.994 ; 5.031 ; 5.796 ; 5.853 ; +; SW[4] ; VGA_R[2] ; 4.913 ; 4.917 ; 5.749 ; 5.753 ; +; SW[4] ; VGA_R[3] ; 4.889 ; 4.891 ; 5.702 ; 5.730 ; +; SW[5] ; VGA_B[0] ; 4.558 ; 4.528 ; 5.361 ; 5.357 ; +; SW[5] ; VGA_B[1] ; 5.040 ; 5.034 ; 5.885 ; 5.879 ; +; SW[5] ; VGA_B[2] ; 4.472 ; 4.453 ; 5.269 ; 5.269 ; +; SW[5] ; VGA_B[3] ; 5.178 ; 5.188 ; 6.044 ; 6.054 ; +; SW[5] ; VGA_G[0] ; 4.645 ; 4.628 ; 5.463 ; 5.465 ; +; SW[5] ; VGA_G[1] ; 5.033 ; 5.053 ; 5.895 ; 5.908 ; +; SW[5] ; VGA_G[2] ; 4.702 ; 4.701 ; 5.519 ; 5.537 ; +; SW[5] ; VGA_G[3] ; 5.120 ; 5.119 ; 5.985 ; 5.979 ; +; SW[5] ; VGA_R[0] ; 4.670 ; 4.664 ; 5.465 ; 5.478 ; +; SW[5] ; VGA_R[1] ; 5.583 ; 5.633 ; 6.472 ; 6.506 ; +; SW[5] ; VGA_R[2] ; 4.707 ; 4.695 ; 5.510 ; 5.524 ; +; SW[5] ; VGA_R[3] ; 5.271 ; 5.289 ; 6.117 ; 6.135 ; ++------------+-------------+-------+-------+-------+-------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Output Enable Times ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 2.588 ; 2.569 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.856 ; 2.837 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.588 ; 2.569 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.598 ; 2.579 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.677 ; 2.658 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.689 ; 2.670 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.588 ; 2.569 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.709 ; 2.690 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.688 ; 2.669 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.876 ; 2.857 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.876 ; 2.857 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.876 ; 2.857 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.866 ; 2.847 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.866 ; 2.847 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.876 ; 2.857 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.856 ; 2.837 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 2.689 ; 2.670 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Minimum Output Enable Times ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 1.467 ; 1.467 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 1.725 ; 1.725 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 1.467 ; 1.467 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 1.477 ; 1.477 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 1.553 ; 1.553 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 1.564 ; 1.564 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 1.467 ; 1.467 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 1.584 ; 1.584 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 1.563 ; 1.563 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 1.745 ; 1.745 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 1.745 ; 1.745 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 1.745 ; 1.745 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 1.735 ; 1.735 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 1.735 ; 1.735 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 1.745 ; 1.745 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 1.725 ; 1.725 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 1.564 ; 1.564 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Output Disable Times ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 2.636 ; 2.636 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.937 ; 2.937 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.636 ; 2.636 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.646 ; 2.646 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.728 ; 2.728 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.752 ; 2.752 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.636 ; 2.636 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.772 ; 2.772 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.749 ; 2.749 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.963 ; 2.963 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.963 ; 2.963 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.957 ; 2.957 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.953 ; 2.953 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.947 ; 2.947 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.957 ; 2.957 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.937 ; 2.937 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 2.752 ; 2.752 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Minimum Output Disable Times ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 1.514 ; 1.646 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 1.802 ; 1.934 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 1.514 ; 1.646 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 1.524 ; 1.656 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 1.601 ; 1.733 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 1.625 ; 1.757 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 1.514 ; 1.646 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 1.645 ; 1.777 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 1.622 ; 1.754 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 1.828 ; 1.960 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 1.828 ; 1.960 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 1.822 ; 1.954 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 1.818 ; 1.950 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 1.812 ; 1.944 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 1.822 ; 1.954 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 1.802 ; 1.934 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 1.625 ; 1.757 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+ + + +---------------- +; MTBF Summary ; +---------------- +Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. +Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + +Number of Synchronizer Chains Found: 40 +Shortest Synchronizer Chain: 2 Registers +Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 +Worst Case Available Settling Time: 13.148 ns + +Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5 +Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9 + + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Synchronizer Summary ; ++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; Source Node ; Synchronization Node ; Worst-Case MTBF (Years) ; Typical MTBF (Years) ; Included in Design MTBF ; ++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; ++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ + + +Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.148 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; ; ; ; 7.315 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; ; ; ; 5.833 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.215 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; ; ; ; 7.592 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; ; ; ; 5.623 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.235 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; ; ; ; 7.593 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; ; ; ; 5.642 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.298 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; ; ; ; 7.311 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; ; ; ; 5.987 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.370 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; ; ; ; 7.525 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; ; ; ; 5.845 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.409 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; ; ; ; 7.588 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; ; ; ; 5.821 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.442 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; ; ; ; 7.589 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; ; ; ; 5.853 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.454 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; ; ; ; 7.590 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; ; ; ; 5.864 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.572 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; ; ; ; 7.590 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; ; ; ; 5.982 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.583 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; ; ; ; 7.592 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; ; ; ; 5.991 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.594 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; ; ; ; 7.523 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; ; ; ; 6.071 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.634 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; ; ; ; 7.590 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; ; ; ; 6.044 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.643 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; ; ; ; 7.229 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; ; ; ; 6.414 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.668 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; ; ; ; 7.542 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; ; ; ; 6.126 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.676 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; ; ; ; 7.524 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; ; ; ; 6.152 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.711 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; ; ; ; 7.525 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; ; ; ; 6.186 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.718 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; ; ; ; 7.591 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; ; ; ; 6.127 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.731 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; ; ; ; 7.600 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; ; ; ; 6.131 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.752 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; ; ; ; 7.526 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; ; ; ; 6.226 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.761 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; ; ; ; 7.401 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; ; ; ; 6.360 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.838 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; ; ; ; 7.453 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; ; ; ; 6.385 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.845 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; ; ; ; 7.402 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; ; ; ; 6.443 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.845 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; ; ; ; 7.526 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; ; ; ; 6.319 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.869 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; ; ; ; 7.510 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; ; ; ; 6.359 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.911 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; ; ; ; 7.532 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; ; ; ; 6.379 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.914 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; ; ; ; 7.401 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; ; ; ; 6.513 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.923 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; ; ; ; 7.456 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; ; ; ; 6.467 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.923 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; ; ; ; 7.525 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; ; ; ; 6.398 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.942 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; ; ; ; 7.444 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; ; ; ; 6.498 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.951 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; ; ; ; 7.535 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; ; ; ; 6.416 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.978 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; ; ; ; 7.528 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; ; ; ; 6.450 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.982 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; ; ; ; 7.442 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; ; ; ; 6.540 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 13.990 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; ; ; ; 7.523 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; ; ; ; 6.467 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 14.000 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; ; ; ; 7.527 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; ; ; ; 6.473 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 14.002 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; ; ; ; 7.513 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; ; ; ; 6.489 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 14.031 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; ; ; ; 7.591 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; ; ; ; 6.440 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 14.093 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; ; ; ; 7.524 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; ; ; ; 6.569 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 14.094 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; ; ; ; 7.524 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; ; ; ; 6.570 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 14.146 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; ; ; ; 7.404 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; ; ; ; 6.742 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; +; Synchronization Node ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 14.159 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 15.63 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ; 8.000 ; 125.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; ; ; ; 7.440 ; +; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; ; ; ; 6.719 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + ++-------------------------------------------------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------------------------------------------+---------+-------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------------------------------------------+---------+-------+----------+---------+---------------------+ +; Worst-case Slack ; -0.490 ; 0.170 ; -1.484 ; 0.851 ; 3.733 ; +; CLOCK_50 ; 14.792 ; 0.188 ; 14.000 ; 0.851 ; 9.267 ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -0.490 ; 0.170 ; -1.484 ; 2.398 ; 3.733 ; +; Design-wide TNS ; -24.984 ; 0.0 ; -348.952 ; 0.0 ; 0.0 ; +; CLOCK_50 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -24.984 ; 0.000 ; -348.952 ; 0.000 ; 0.000 ; ++------------------------------------------------------+---------+-------+----------+---------+---------------------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Setup Times ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ +; SW[*] ; CLOCK_50 ; 4.162 ; 4.886 ; Rise ; CLOCK_50 ; +; SW[0] ; CLOCK_50 ; 4.162 ; 4.886 ; Rise ; CLOCK_50 ; +; SW[1] ; CLOCK_50 ; 4.039 ; 4.609 ; Rise ; CLOCK_50 ; +; DRAM_DQ[*] ; CLOCK_50 ; 4.195 ; 4.756 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 3.989 ; 4.558 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 3.703 ; 4.276 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 3.849 ; 4.364 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 3.867 ; 4.442 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 4.195 ; 4.756 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 3.689 ; 4.201 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 3.971 ; 4.530 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 3.696 ; 4.203 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 3.713 ; 4.224 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 3.663 ; 4.241 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 3.721 ; 4.230 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 3.722 ; 4.233 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 3.874 ; 4.393 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 3.710 ; 4.224 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 3.905 ; 4.446 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+-----------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------+ +; Hold Times ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ +; SW[*] ; CLOCK_50 ; -1.138 ; -1.987 ; Rise ; CLOCK_50 ; +; SW[0] ; CLOCK_50 ; -1.174 ; -2.007 ; Rise ; CLOCK_50 ; +; SW[1] ; CLOCK_50 ; -1.138 ; -1.987 ; Rise ; CLOCK_50 ; +; DRAM_DQ[*] ; CLOCK_50 ; -1.725 ; -2.460 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; -1.890 ; -2.688 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; -1.745 ; -2.526 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; -1.811 ; -2.549 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; -1.842 ; -2.630 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; -1.997 ; -2.818 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; -1.730 ; -2.464 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; -1.899 ; -2.681 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; -1.725 ; -2.460 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; -1.751 ; -2.485 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; -1.733 ; -2.513 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; -1.752 ; -2.489 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; -1.748 ; -2.486 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; -1.839 ; -2.575 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; -1.746 ; -2.481 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; -1.852 ; -2.606 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------+ +; Clock to Output Times ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; GPIO_1[*] ; CLOCK_50 ; 6.431 ; 6.267 ; Rise ; CLOCK_50 ; +; GPIO_1[14] ; CLOCK_50 ; 6.284 ; 6.232 ; Rise ; CLOCK_50 ; +; GPIO_1[20] ; CLOCK_50 ; 6.431 ; 6.267 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[*] ; CLOCK_50 ; 5.650 ; 5.688 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[0] ; CLOCK_50 ; 5.650 ; 5.688 ; Rise ; CLOCK_50 ; +; VGA_CLK ; CLOCK_50 ; 5.538 ; 5.554 ; Rise ; CLOCK_50 ; +; DRAM_ADDR[*] ; CLOCK_50 ; 3.434 ; 3.299 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[0] ; CLOCK_50 ; 3.430 ; 3.281 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[1] ; CLOCK_50 ; 3.434 ; 3.299 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[2] ; CLOCK_50 ; 3.410 ; 3.272 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[3] ; CLOCK_50 ; 3.410 ; 3.280 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[4] ; CLOCK_50 ; 3.228 ; 3.089 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[5] ; CLOCK_50 ; 3.207 ; 3.075 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[6] ; CLOCK_50 ; 3.040 ; 2.920 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[7] ; CLOCK_50 ; 3.050 ; 2.930 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[8] ; CLOCK_50 ; 3.042 ; 2.918 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[9] ; CLOCK_50 ; 3.035 ; 2.919 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[10] ; CLOCK_50 ; 3.278 ; 3.155 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[11] ; CLOCK_50 ; 3.026 ; 2.912 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_0 ; CLOCK_50 ; 3.104 ; 3.009 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_1 ; CLOCK_50 ; 3.264 ; 3.154 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CAS_N ; CLOCK_50 ; 3.210 ; 3.078 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CS_N ; CLOCK_50 ; 3.582 ; 3.529 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[*] ; CLOCK_50 ; 7.477 ; 7.147 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 5.872 ; 5.694 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 5.872 ; 5.846 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 5.578 ; 5.489 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 7.477 ; 7.147 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 5.679 ; 5.582 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 5.894 ; 5.773 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 5.858 ; 5.642 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 5.792 ; 5.739 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 5.729 ; 5.636 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 5.790 ; 5.709 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 5.922 ; 5.821 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 5.990 ; 5.797 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 6.015 ; 5.897 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 5.995 ; 5.873 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 5.870 ; 5.693 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 5.824 ; 5.740 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_LDQM ; CLOCK_50 ; 3.456 ; 3.316 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_RAS_N ; CLOCK_50 ; 3.401 ; 3.282 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_UDQM ; CLOCK_50 ; 3.348 ; 3.248 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 5.256 ; 4.904 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CLK ; CLOCK_50 ; -0.448 ; ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; +; DRAM_CLK ; CLOCK_50 ; ; -0.595 ; Fall ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ +; GPIO_1[*] ; CLOCK_50 ; 3.685 ; 3.643 ; Rise ; CLOCK_50 ; +; GPIO_1[14] ; CLOCK_50 ; 3.685 ; 3.753 ; Rise ; CLOCK_50 ; +; GPIO_1[20] ; CLOCK_50 ; 3.686 ; 3.643 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[*] ; CLOCK_50 ; 3.286 ; 3.374 ; Rise ; CLOCK_50 ; +; GPIO_1_CLKOUT[0] ; CLOCK_50 ; 3.286 ; 3.374 ; Rise ; CLOCK_50 ; +; VGA_CLK ; CLOCK_50 ; 3.266 ; 3.193 ; Rise ; CLOCK_50 ; +; DRAM_ADDR[*] ; CLOCK_50 ; 1.574 ; 1.532 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[0] ; CLOCK_50 ; 1.789 ; 1.764 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[1] ; CLOCK_50 ; 1.806 ; 1.779 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[2] ; CLOCK_50 ; 1.794 ; 1.763 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[3] ; CLOCK_50 ; 1.787 ; 1.756 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[4] ; CLOCK_50 ; 1.694 ; 1.661 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[5] ; CLOCK_50 ; 1.674 ; 1.636 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[6] ; CLOCK_50 ; 1.585 ; 1.542 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[7] ; CLOCK_50 ; 1.595 ; 1.553 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[8] ; CLOCK_50 ; 1.574 ; 1.532 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[9] ; CLOCK_50 ; 1.584 ; 1.542 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[10] ; CLOCK_50 ; 1.725 ; 1.696 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[11] ; CLOCK_50 ; 1.575 ; 1.533 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_0 ; CLOCK_50 ; 1.634 ; 1.607 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA_1 ; CLOCK_50 ; 1.720 ; 1.702 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CAS_N ; CLOCK_50 ; 1.670 ; 1.640 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CS_N ; CLOCK_50 ; 1.883 ; 1.893 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[*] ; CLOCK_50 ; 2.138 ; 2.126 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.138 ; 2.126 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.630 ; 2.712 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.422 ; 2.456 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 3.881 ; 3.708 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.479 ; 2.515 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.549 ; 2.620 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.472 ; 2.507 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.545 ; 2.606 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.366 ; 2.385 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.394 ; 2.422 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.457 ; 2.478 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.394 ; 2.427 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.622 ; 2.676 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.497 ; 2.535 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.304 ; 2.306 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 2.395 ; 2.416 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_LDQM ; CLOCK_50 ; 1.803 ; 1.779 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_RAS_N ; CLOCK_50 ; 1.770 ; 1.747 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_UDQM ; CLOCK_50 ; 1.772 ; 1.752 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 3.215 ; 2.983 ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CLK ; CLOCK_50 ; -1.537 ; ; Rise ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; +; DRAM_CLK ; CLOCK_50 ; ; -1.591 ; Fall ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; ++-------------------+------------+--------+--------+------------+-----------------------------------------------------+ + + ++------------------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+-------+-------+--------+--------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+--------+--------+ +; SW[4] ; VGA_B[0] ; 8.598 ; 8.436 ; 9.243 ; 9.072 ; +; SW[4] ; VGA_B[1] ; 8.447 ; 8.325 ; 9.042 ; 8.914 ; +; SW[4] ; VGA_B[2] ; 8.575 ; 8.414 ; 9.221 ; 9.051 ; +; SW[4] ; VGA_B[3] ; 8.667 ; 8.584 ; 9.283 ; 9.242 ; +; SW[4] ; VGA_G[0] ; 8.652 ; 8.475 ; 9.234 ; 9.066 ; +; SW[4] ; VGA_G[1] ; 9.016 ; 8.875 ; 9.652 ; 9.511 ; +; SW[4] ; VGA_G[2] ; 8.756 ; 8.632 ; 9.342 ; 9.227 ; +; SW[4] ; VGA_G[3] ; 9.210 ; 9.093 ; 9.844 ; 9.730 ; +; SW[4] ; VGA_R[0] ; 8.916 ; 8.791 ; 9.563 ; 9.429 ; +; SW[4] ; VGA_R[1] ; 9.140 ; 9.076 ; 9.701 ; 9.628 ; +; SW[4] ; VGA_R[2] ; 8.626 ; 8.470 ; 9.215 ; 9.063 ; +; SW[4] ; VGA_R[3] ; 8.836 ; 8.685 ; 9.435 ; 9.279 ; +; SW[5] ; VGA_B[0] ; 8.150 ; 7.979 ; 8.767 ; 8.596 ; +; SW[5] ; VGA_B[1] ; 8.882 ; 8.754 ; 9.475 ; 9.347 ; +; SW[5] ; VGA_B[2] ; 8.247 ; 8.086 ; 8.912 ; 8.742 ; +; SW[5] ; VGA_B[3] ; 9.227 ; 9.142 ; 9.829 ; 9.788 ; +; SW[5] ; VGA_G[0] ; 8.549 ; 8.372 ; 9.098 ; 8.924 ; +; SW[5] ; VGA_G[1] ; 9.002 ; 8.861 ; 9.616 ; 9.475 ; +; SW[5] ; VGA_G[2] ; 8.653 ; 8.529 ; 9.203 ; 9.084 ; +; SW[5] ; VGA_G[3] ; 9.192 ; 9.078 ; 9.808 ; 9.694 ; +; SW[5] ; VGA_R[0] ; 8.583 ; 8.458 ; 9.256 ; 9.122 ; +; SW[5] ; VGA_R[1] ; 9.959 ; 9.909 ; 10.554 ; 10.517 ; +; SW[5] ; VGA_R[2] ; 8.412 ; 8.256 ; 9.035 ; 8.879 ; +; SW[5] ; VGA_R[3] ; 9.269 ; 9.113 ; 9.869 ; 9.713 ; ++------------+-------------+-------+-------+--------+--------+ + + ++----------------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; SW[4] ; VGA_B[0] ; 4.871 ; 4.857 ; 5.715 ; 5.701 ; +; SW[4] ; VGA_B[1] ; 4.662 ; 4.640 ; 5.472 ; 5.476 ; +; SW[4] ; VGA_B[2] ; 4.854 ; 4.839 ; 5.699 ; 5.684 ; +; SW[4] ; VGA_B[3] ; 4.588 ; 4.587 ; 5.391 ; 5.410 ; +; SW[4] ; VGA_G[0] ; 4.860 ; 4.847 ; 5.716 ; 5.696 ; +; SW[4] ; VGA_G[1] ; 4.861 ; 4.865 ; 5.688 ; 5.718 ; +; SW[4] ; VGA_G[2] ; 4.920 ; 4.923 ; 5.775 ; 5.771 ; +; SW[4] ; VGA_G[3] ; 4.699 ; 4.697 ; 5.557 ; 5.518 ; +; SW[4] ; VGA_R[0] ; 5.048 ; 5.046 ; 5.894 ; 5.892 ; +; SW[4] ; VGA_R[1] ; 4.994 ; 5.031 ; 5.796 ; 5.853 ; +; SW[4] ; VGA_R[2] ; 4.913 ; 4.917 ; 5.749 ; 5.753 ; +; SW[4] ; VGA_R[3] ; 4.889 ; 4.891 ; 5.702 ; 5.730 ; +; SW[5] ; VGA_B[0] ; 4.558 ; 4.528 ; 5.361 ; 5.357 ; +; SW[5] ; VGA_B[1] ; 5.040 ; 5.034 ; 5.885 ; 5.879 ; +; SW[5] ; VGA_B[2] ; 4.472 ; 4.453 ; 5.269 ; 5.269 ; +; SW[5] ; VGA_B[3] ; 5.178 ; 5.188 ; 6.044 ; 6.054 ; +; SW[5] ; VGA_G[0] ; 4.645 ; 4.628 ; 5.463 ; 5.465 ; +; SW[5] ; VGA_G[1] ; 5.033 ; 5.053 ; 5.895 ; 5.908 ; +; SW[5] ; VGA_G[2] ; 4.702 ; 4.701 ; 5.519 ; 5.537 ; +; SW[5] ; VGA_G[3] ; 5.120 ; 5.119 ; 5.985 ; 5.979 ; +; SW[5] ; VGA_R[0] ; 4.670 ; 4.664 ; 5.465 ; 5.478 ; +; SW[5] ; VGA_R[1] ; 5.583 ; 5.633 ; 6.472 ; 6.506 ; +; SW[5] ; VGA_R[2] ; 4.707 ; 4.695 ; 5.510 ; 5.524 ; +; SW[5] ; VGA_R[3] ; 5.271 ; 5.289 ; 6.117 ; 6.135 ; ++------------+-------------+-------+-------+-------+-------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; DRAM_LDQM ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_UDQM ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_BA_1 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_BA_0 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_CAS_N ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_CKE ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_CS_N ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_RAS_N ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_WE_N ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_CLK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_CLK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_HS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_VS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[11] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[10] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1_CLKOUT[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1_CLKOUT[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_B[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_B[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_B[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_B[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_G[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_G[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_G[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_G[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_R[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_R[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_R[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; VGA_R[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[15] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[14] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[13] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[12] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[11] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[10] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[31] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[30] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[29] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[28] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[27] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[26] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[25] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[24] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[23] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[22] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[21] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[20] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[19] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[18] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[17] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[16] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[15] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[14] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[13] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[12] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[11] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[10] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; PS2_DAT ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; PS2_CLK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++----------------------------------------------------------------------------+ +; Input Transition Times ; ++-------------------------+--------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++-------------------------+--------------+-----------------+-----------------+ +; GPIO_1_CLKIN[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[9] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[8] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[15] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[14] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[13] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[12] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[11] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[10] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[9] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[8] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DRAM_DQ[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[31] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[30] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[29] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[28] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[27] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[26] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[25] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[24] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[23] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[22] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[21] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[20] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[19] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[18] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[17] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[16] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[15] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[14] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[13] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[12] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[11] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[10] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[9] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[8] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; PS2_DAT ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; PS2_CLK ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; CLOCK_50 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; KEY[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; KEY[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO_1_CLKIN[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; KEY[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ~ALTERA_ASDO_DATA1~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ~ALTERA_DATA0~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ++-------------------------+--------------+-----------------+-----------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow Corner Signal Integrity Metrics ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; DRAM_LDQM ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_UDQM ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_BA_1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_BA_0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_CAS_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_CKE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_CS_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_RAS_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_WE_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.08 V ; -0.00596 V ; 0.305 V ; 0.266 V ; 5.3e-09 s ; 4.39e-09 s ; Yes ; Yes ; 3.08 V ; 3.08e-06 V ; 3.08 V ; -0.00596 V ; 0.305 V ; 0.266 V ; 5.3e-09 s ; 4.39e-09 s ; Yes ; Yes ; +; DRAM_CLK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; VGA_CLK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; VGA_HS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_VS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; DRAM_ADDR[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_ADDR[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1_CLKOUT[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1_CLKOUT[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX3[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; HEX3[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; LEDG[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; LEDG[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; LEDG[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; LEDG[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; LEDG[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; LEDG[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; LEDG[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; LEDG[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.08 V ; -0.00513 V ; 0.274 V ; 0.267 V ; 5.67e-09 s ; 4.62e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.08 V ; -0.00513 V ; 0.274 V ; 0.267 V ; 5.67e-09 s ; 4.62e-09 s ; No ; Yes ; +; LEDG[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; LEDG[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_B[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_B[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_B[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_B[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_G[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_G[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_G[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_G[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_R[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_R[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_R[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; VGA_R[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; DRAM_DQ[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.08 V ; -0.00596 V ; 0.305 V ; 0.266 V ; 5.3e-09 s ; 4.39e-09 s ; Yes ; Yes ; 3.08 V ; 3.08e-06 V ; 3.08 V ; -0.00596 V ; 0.305 V ; 0.266 V ; 5.3e-09 s ; 4.39e-09 s ; Yes ; Yes ; +; DRAM_DQ[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; DRAM_DQ[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[31] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[30] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[29] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[28] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[27] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[26] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[25] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[24] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[23] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[22] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[21] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[20] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[19] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[18] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[17] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[16] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; GPIO_1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; 3.08 V ; 3.08e-06 V ; 3.13 V ; -0.0523 V ; 0.237 V ; 0.168 V ; 6.67e-10 s ; 6.11e-10 s ; No ; No ; +; PS2_DAT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; PS2_CLK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; 3.08 V ; 2.06e-06 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-09 s ; 1.07e-09 s ; No ; Yes ; +; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.02e-06 V ; 3.14 V ; -0.0402 V ; 0.146 V ; 0.156 V ; 4.62e-10 s ; 4.36e-10 s ; Yes ; Yes ; 3.08 V ; 1.02e-06 V ; 3.14 V ; -0.0402 V ; 0.146 V ; 0.156 V ; 4.62e-10 s ; 4.36e-10 s ; Yes ; Yes ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast Corner Signal Integrity Metrics ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; DRAM_LDQM ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_UDQM ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_BA_1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_BA_0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_CAS_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_CKE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_CS_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_RAS_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_WE_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.48 V ; -0.0142 V ; 0.362 V ; 0.291 V ; 3.89e-09 s ; 3.25e-09 s ; No ; No ; 3.46 V ; 1.9e-07 V ; 3.48 V ; -0.0142 V ; 0.362 V ; 0.291 V ; 3.89e-09 s ; 3.25e-09 s ; No ; No ; +; DRAM_CLK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; VGA_CLK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; VGA_HS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_VS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; DRAM_ADDR[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_ADDR[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1_CLKOUT[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1_CLKOUT[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX0[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX0[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX0[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX3[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; HEX3[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; LEDG[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; LEDG[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; LEDG[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; LEDG[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; LEDG[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; LEDG[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; LEDG[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; LEDG[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.346 V ; 4.12e-09 s ; 3.34e-09 s ; No ; Yes ; 3.46 V ; 1.29e-07 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.346 V ; 4.12e-09 s ; 3.34e-09 s ; No ; Yes ; +; LEDG[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; LEDG[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_B[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_B[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_B[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_B[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_G[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_G[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_G[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_G[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_R[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_R[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_R[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; VGA_R[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; DRAM_DQ[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.48 V ; -0.0142 V ; 0.362 V ; 0.291 V ; 3.89e-09 s ; 3.25e-09 s ; No ; No ; 3.46 V ; 1.9e-07 V ; 3.48 V ; -0.0142 V ; 0.362 V ; 0.291 V ; 3.89e-09 s ; 3.25e-09 s ; No ; No ; +; DRAM_DQ[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; DRAM_DQ[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[31] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[30] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[29] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[28] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[27] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[26] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[25] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[24] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[23] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[22] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[21] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[20] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[19] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[18] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[17] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[16] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; GPIO_1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; 3.46 V ; 1.9e-07 V ; 3.59 V ; -0.0873 V ; 0.332 V ; 0.189 V ; 4.6e-10 s ; 4.2e-10 s ; No ; Yes ; +; PS2_DAT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; PS2_CLK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; 3.46 V ; 1.29e-07 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.35 V ; 9.04e-10 s ; 7.28e-10 s ; No ; No ; +; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.52e-08 V ; 3.58 V ; -0.064 V ; 0.234 V ; 0.085 V ; 2.93e-10 s ; 3.07e-10 s ; Yes ; Yes ; 3.46 V ; 6.52e-08 V ; 3.58 V ; -0.064 V ; 0.234 V ; 0.085 V ; 2.93e-10 s ; 3.07e-10 s ; Yes ; Yes ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Setup Transfers ; ++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+ +; CLOCK_50 ; CLOCK_50 ; 3231 ; 0 ; 0 ; 0 ; +; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 141 ; 0 ; 0 ; 0 ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 11699 ; 0 ; 0 ; 0 ; ++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Hold Transfers ; ++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+ +; CLOCK_50 ; CLOCK_50 ; 3231 ; 0 ; 0 ; 0 ; +; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 141 ; 0 ; 0 ; 0 ; +; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 11699 ; 0 ; 0 ; 0 ; ++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++--------------------------------------------------------------------------------------------------------------+ +; Recovery Transfers ; ++------------+-----------------------------------------------------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+-----------------------------------------------------+----------+----------+----------+----------+ +; CLOCK_50 ; CLOCK_50 ; 519 ; 0 ; 0 ; 0 ; +; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 302 ; 0 ; 0 ; 0 ; ++------------+-----------------------------------------------------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++--------------------------------------------------------------------------------------------------------------+ +; Removal Transfers ; ++------------+-----------------------------------------------------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+-----------------------------------------------------+----------+----------+----------+----------+ +; CLOCK_50 ; CLOCK_50 ; 519 ; 0 ; 0 ; 0 ; +; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 302 ; 0 ; 0 ; 0 ; ++------------+-----------------------------------------------------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 5 ; 5 ; +; Unconstrained Input Ports ; 43 ; 43 ; +; Unconstrained Input Port Paths ; 428 ; 428 ; +; Unconstrained Output Ports ; 89 ; 89 ; +; Unconstrained Output Port Paths ; 530 ; 530 ; ++---------------------------------+-------+------+ + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer + Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version + Info: Processing started: Mon Mar 17 11:17:27 2014 +Info: Command: quartus_sta DE0_D5M -c DE0_D5M +Info: qsta_default_script.tcl version: #1 +Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead. +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (332164): Evaluating HDL-embedded SDC commands + Info (332165): Entity dcfifo_v5o1 + Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a* + Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a* +Info (332104): Reading SDC File: 'DE0_D5M.sdc' +Info (332110): Deriving PLL clocks + Info (332110): create_generated_clock -source {inst|u6|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name {inst|u6|altpll_component|auto_generated|pll1|clk[0]} {inst|u6|altpll_component|auto_generated|pll1|clk[0]} + Info (332110): create_generated_clock -source {inst|u6|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 5 -phase -117.00 -duty_cycle 50.00 -name {inst|u6|altpll_component|auto_generated|pll1|clk[1]} {inst|u6|altpll_component|auto_generated|pll1|clk[1]} +Warning (332060): Node: ps2:inst6|clk_div[8] was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: ps2:inst6|ps2_clk_in was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment. +Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. + Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold) + Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold) + Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold) +Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info: Analyzing Slow 1200mV 85C Model +Critical Warning (332148): Timing requirements not met + Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. +Info (332146): Worst-case setup slack is -0.490 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -0.490 -24.984 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 14.792 0.000 CLOCK_50 +Info (332146): Worst-case hold slack is 0.332 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.332 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 0.358 0.000 CLOCK_50 +Info (332146): Worst-case recovery slack is -1.484 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -1.484 -348.952 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 14.000 0.000 CLOCK_50 +Info (332146): Worst-case removal slack is 1.548 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 1.548 0.000 CLOCK_50 + Info (332119): 4.100 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case minimum pulse width slack is 3.733 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 3.733 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 9.580 0.000 CLOCK_50 +Info (332114): Report Metastability: Found 40 synchronizer chains. + Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. + Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + + Info (332114): Number of Synchronizer Chains Found: 40 + Info (332114): Shortest Synchronizer Chain: 2 Registers + Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 + Info (332114): Worst Case Available Settling Time: 10.993 ns + Info (332114): + Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5 + Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9 +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Warning (332060): Node: ps2:inst6|clk_div[8] was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: ps2:inst6|ps2_clk_in was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment. +Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. + Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold) + Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold) + Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold) +Info (332146): Worst-case setup slack is 0.022 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.022 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 15.359 0.000 CLOCK_50 +Info (332146): Worst-case hold slack is 0.298 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.298 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 0.312 0.000 CLOCK_50 +Critical Warning (332148): Timing requirements not met + Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. +Info (332146): Worst-case recovery slack is -0.828 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -0.828 -158.364 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 14.667 0.000 CLOCK_50 +Info (332146): Worst-case removal slack is 1.412 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 1.412 0.000 CLOCK_50 + Info (332119): 3.602 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case minimum pulse width slack is 3.739 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 3.739 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 9.562 0.000 CLOCK_50 +Info (332114): Report Metastability: Found 40 synchronizer chains. + Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. + Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + + Info (332114): Number of Synchronizer Chains Found: 40 + Info (332114): Shortest Synchronizer Chain: 2 Registers + Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 + Info (332114): Worst Case Available Settling Time: 11.499 ns + Info (332114): + Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5 + Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9 +Info: Analyzing Fast 1200mV 0C Model +Warning (332060): Node: ps2:inst6|clk_div[8] was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: ps2:inst6|ps2_clk_in was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment. +Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. + Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold) + Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold) + Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold) +Info (332146): Worst-case setup slack is 1.392 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 1.392 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 16.970 0.000 CLOCK_50 +Info (332146): Worst-case hold slack is 0.170 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.170 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 0.188 0.000 CLOCK_50 +Info (332146): Worst-case recovery slack is 0.783 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.783 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 16.478 0.000 CLOCK_50 +Info (332146): Worst-case removal slack is 0.851 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.851 0.000 CLOCK_50 + Info (332119): 2.398 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case minimum pulse width slack is 3.746 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 3.746 0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 9.267 0.000 CLOCK_50 +Info (332114): Report Metastability: Found 40 synchronizer chains. + Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. + Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + + Info (332114): Number of Synchronizer Chains Found: 40 + Info (332114): Shortest Synchronizer Chain: 2 Registers + Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 + Info (332114): Worst Case Available Settling Time: 13.148 ns + Info (332114): + Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5 + Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9 +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 29 warnings + Info: Peak virtual memory: 555 megabytes + Info: Processing ended: Mon Mar 17 11:17:31 2014 + Info: Elapsed time: 00:00:04 + Info: Total CPU time (on all processors): 00:00:04 + + |